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Modified plic and uart to remove async reset. This removes vivado critical warning.

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This commit is contained in:
Ross Thompson 2023-03-24 20:37:48 -05:00
parent c10d98b1c8
commit 3fc0c4b34e
2 changed files with 2 additions and 2 deletions
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2
src/uncore/plic_apb.sv
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@ -97,7 +97,7 @@ module plic_apb (
// ================== // ==================
// Register Interface // Register Interface
// ================== // ==================
always @(posedge PCLK,negedge PRESETn) begin always @(posedge PCLK) begin
// resetting // resetting
if (~PRESETn) begin if (~PRESETn) begin
intPriority <= #1 {`N{3'b0}}; intPriority <= #1 {`N{3'b0}};

2
src/uncore/uartPC16550D.sv
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@ -290,7 +290,7 @@ module uartPC16550D(
assign rxbreak = rxframingerr & (rxdata9 == 9'b0); // break when 0 for start + data + parity + stop time assign rxbreak = rxframingerr & (rxdata9 == 9'b0); // break when 0 for start + data + parity + stop time
// receive FIFO and register // receive FIFO and register
always_ff @(posedge PCLK, negedge PRESETn) always_ff @(posedge PCLK)
if (~PRESETn) begin if (~PRESETn) begin
rxfifohead <= #1 0; rxfifotail <= #1 0; rxdataready <= #1 0; RXBR <= #1 0; rxfifohead <= #1 0; rxfifotail <= #1 0; rxdataready <= #1 0; RXBR <= #1 0;
end else begin end else begin