Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

wally-pipelined/config/buildroot/wally-config.vh

@@ -31,6 +31,7 @@
 `define BUSYBEAR 0
 `define LINUX_FIX_READ {'h10000005}
 `define LINUX_TEST_VECTORS "../linux-testgen/linux-testvectors/"
+//`define LINUX_TEST_VECTORS "/courses/e190ax/buildroot_boot/"
 // RV32 or RV64: XLEN = 32 or 64
 `define XLEN 64
 

wally-pipelined/linux-testgen/testvector-generation/debugBuildroot.sh

@@ -23,7 +23,7 @@ outDir="../linux-testvectors"
 # Uncomment this version to generate qemu_output.txt
 # - Uses GDB script
 # - Logs raw QEMU output to qemu_output.txt
-#($customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -gdb tcp::1237 -S 2> $intermedDir/qemu_output.txt) & riscv64-unknown-elf-gdb -x gdbinit_debug
+($customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -gdb tcp::1237 -S 2> $intermedDir/qemu_output.txt) & riscv64-unknown-elf-gdb -x gdbinit_debug
 
 # Uncomment this version for parse_qemu.py debugging
 # - Uses qemu_output.txt

wally-pipelined/linux-testgen/testvector-generation/fix_csrs.py

@@ -0,0 +1,28 @@
+#! /usr/bin/python3
+import sys, fileinput
+
+sys.stderr.write("reminder: fix_csrs.py is nothing but hardcoded hackery to combat QEMU's faulty printing")
+
+csrs = ['fcsr','mcause','mcounteren','medeleg','mepc','mhartid','mideleg','mie','mip','misa','mscratch','mstatus','mtval','mtvec','pmpaddr0','pmpcfg0','satp','scause','scounteren','sepc','sie','sscratch','sstatus','stval','stvec']
+
+# just for now, since these CSRs aren't yet ready to be checked in testbench-linux
+list(map(csrs.remove, ['fcsr','mhartid','pmpcfg0','pmpaddr0','mip']))
+output_path = sys.argv[1]+'/'
+print(f'output dir: {output_path}')
+count = 0
+csr = ''
+with open('{}parsedCSRs.txt'.format(output_path), 'w') as fixedCSRs:
+    with open('{}/intermediate-outputs/unfixedParsedCSRs.txt'.format(output_path), 'r') as rawCSRs:
+      for l in rawCSRs:
+          fixedCSRs.write(l)
+          count += 1
+          if '---' in l:
+              count = 0
+          if (count%2 == 1): # every other line is CSR name
+              csr = l
+          else:
+              if ('stval' in csr) and ('8020007e' in l):
+                  print('Adding stvec vector')
+                  fixedCSRs.write('stvec\n')
+                  fixedCSRs.write('ffffffff800000b0\n')
+          

wally-pipelined/linux-testgen/testvector-generation/gdbinit_qemulog

@@ -1,11 +1,11 @@
 set pagination off
 target extended-remote :1236
 file ../buildroot-image-output/vmlinux
+stepi 1000
 b do_idle
 c
 c
 c
-c
 set confirm off
 kill
 q

wally-pipelined/linux-testgen/testvector-generation/logAllBuildroot.sh

@@ -12,3 +12,4 @@ outDir="../linux-testvectors"
 
 # - Logs info needed by buildroot testbench
 ($customQemu -M virt -nographic -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio -d nochain,cpu,in_asm -serial /dev/null -singlestep -gdb tcp::1236 -S 2>&1 >/dev/null | ./parse_qemu.py | ./parse_gdb_output.py "$outDir") & riscv64-unknown-elf-gdb -x gdbinit_qemulog
+./fix_csrs.py "$outDir"

wally-pipelined/linux-testgen/testvector-generation/parse_gdb_output.py

@@ -1,7 +1,7 @@
 #! /usr/bin/python3
 import sys, fileinput
 
-sys.stderr.write("reminder: this script takes input from stdin\n")
+sys.stderr.write("reminder: parse_gdb_output.py takes input from stdin\n")
 
 csrs = ['fcsr','mcause','mcounteren','medeleg','mepc','mhartid','mideleg','mie','mip','misa','mscratch','mstatus','mtval','mtvec','pmpaddr0','pmpcfg0','satp','scause','scounteren','sepc','sie','sscratch','sstatus','stval','stvec']
 
@@ -17,7 +17,7 @@ try:
       with open('{}parsedRegs.txt'.format(output_path), 'w') as wReg:
         with open('{}parsedMemRead.txt'.format(output_path), 'w') as wMem:
           with open('{}parsedMemWrite.txt'.format(output_path), 'w') as wMemW:
-            with open('{}parsedCSRs.txt'.format(output_path), 'w') as wCSRs:
+            with open('{}/intermediate-outputs/unfixedParsedCSRs.txt'.format(output_path), 'w') as wCSRs:
               firstCSR = True
               curCSRs = {}
               lastRead = ''

wally-pipelined/linux-testgen/testvector-generation/parse_qemu.py

@@ -1,7 +1,7 @@
 #! /usr/bin/python3
 import fileinput, sys
 
-sys.stderr.write("reminder: this script takes input from stdin\n")
+sys.stderr.write("reminder: parse_qemu.py takes input from stdin\n")
 parseState = "idle"
 beginPageFault = 0
 inPageFault = 0
@@ -94,7 +94,6 @@ def parseRegs(l):
                 val = int(s[i+1], 16)
                 if inPageFault:
                     pageFaultRegs[reg] = val
-                    sys.stderr.write(str(pageFaultRegs))
                 else:
                     if pageFaultRegs and (reg in pageFaultRegs):
                         if (val != pageFaultRegs[reg]):

wally-pipelined/src/uncore/uartPC16550D.sv

@@ -269,7 +269,7 @@ module uartPC16550D(
         rxdataready <= #1 1;
       end else if (~MEMRb & A == 3'b000 & ~DLAB) begin // reading RBR updates ready / pops fifo 
         if (fifoenabled) begin
-          rxfifotail <= #1 rxfifotail + 1;
+          if (rxfifotail+1 < rxfifohead) rxfifotail <= #1 rxfifotail + 1;
           if (rxfifohead == rxfifotail +1) rxdataready <= #1 0;
         end else rxdataready <= #1 0;
       end else if (~MEMWb & A == 3'b010)  // writes to FIFO Control Register

wally-pipelined/testbench/testbench-linux.sv

@@ -448,10 +448,14 @@ module testbench();
       scan_file_memR = $fscanf(data_file_memR, "%x\n", readAdrExpected);
       scan_file_memR = $fscanf(data_file_memR, "%x\n", readDataExpected);
       assign readAdrTranslated = adrTranslator(readAdrExpected);
-      if (~(dut.hart.lsu.dcache.MemPAdrM === readAdrTranslated)) begin
+      if (~(dut.hart.ieu.MemAdrM === readAdrExpected)) begin
-        $display("%0t ps, InstrNum %0d, PCM %x, InstrM %s: MemPAdrM does not equal readAdrExpected: %x, %x", $time, instrs, dut.hart.ifu.PCM, PCtextM, dut.hart.lsu.dcache.MemPAdrM, readAdrTranslated);
+        $display("%0t ps, InstrNum %0d, PCM %x, InstrM %s: MemAdrM does not equal virtual readAdrExpected: %x, %x", $time, instrs, dut.hart.ifu.PCM, PCtextM, dut.hart.ieu.MemAdrM, readAdrExpected);
         `ERROR
       end
+      //if (~(dut.hart.lsu.dcache.MemPAdrM === readAdrTranslated)) begin
+      //  $display("%0t ps, InstrNum %0d, PCM %x, InstrM %s: MemPAdrM does not equal physical readAdrExpected: %x, %x", $time, instrs, dut.hart.ifu.PCM, PCtextM, dut.hart.lsu.dcache.MemPAdrM, readAdrTranslated);
+      //  `ERROR
+      //end
       if (readDataExpected !== dut.hart.lsu.dcache.ReadDataM) begin
         if (dut.hart.lsu.dcache.MemPAdrM inside `LINUX_FIX_READ) begin
           if (dut.hart.lsu.dcache.MemPAdrM != 'h10000005) // Suppress the warning for UART LSR so we can read UART output
@@ -479,15 +483,18 @@ module testbench();
       scan_file_memW = $fscanf(data_file_memW, "%x\n", writeDataExpected);
       scan_file_memW = $fscanf(data_file_memW, "%x\n", writeAdrExpected);
       assign writeAdrTranslated = adrTranslator(writeAdrExpected);
-
+      if (~(dut.hart.ieu.MemAdrM === writeAdrExpected)) begin
+        $display("%0t ps, InstrNum %0d, PCM %x, InstrM %s: MemAdrM does not equal virtual writeAdrExpected: %x, %x", $time, instrs, dut.hart.ifu.PCM, PCtextM, dut.hart.ieu.MemAdrM, writeAdrExpected);
+        `ERROR
+      end
       if (writeDataExpected != dut.hart.lsu.dcache.WriteDataM && ~dut.uncore.HSELPLICD) begin
         $display("%0t ps, InstrNum %0d, PCM %x, InstrM %s: WriteDataM does not equal writeDataExpected: %x, %x", $time, instrs, dut.hart.ifu.PCM, PCtextM, dut.hart.lsu.dcache.WriteDataM, writeDataExpected);
         `ERROR
       end
-      if (~(writeAdrTranslated === dut.hart.lsu.dcache.MemPAdrM) && ~dut.uncore.HSELPLICD) begin
+      //if (~(writeAdrTranslated === dut.hart.lsu.dcache.MemPAdrM) && ~dut.uncore.HSELPLICD) begin
-        $display("%0t ps, InstrNum %0d, PCM %x, InstrM %s: MemPAdrM does not equal writeAdrExpected: %x, %x", $time, instrs, dut.hart.ifu.PCM, PCtextM, dut.hart.lsu.dcache.MemPAdrM, writeAdrTranslated);
+      //  $display("%0t ps, InstrNum %0d, PCM %x, InstrM %s: MemPAdrM does not equal physical writeAdrExpected: %x, %x", $time, instrs, dut.hart.ifu.PCM, PCtextM, dut.hart.lsu.dcache.MemPAdrM, writeAdrTranslated);
-        `ERROR
+      //  `ERROR
-      end
+      //end
     end
   end
 
@@ -663,14 +670,14 @@ module testbench();
    * See section 4.3.2 of the RISC-V Privileged specification for a full
    * explanation of the below algorithm.
    */
+  logic             SvMode, PTE_R, PTE_X;
+  logic [`XLEN-1:0] SATP, PTE;
+  logic [55:0]      BaseAdr, PAdr;
+  logic [8:0]       VPN [2:0];
+  logic [11:0]      Offset;
   function logic [`XLEN-1:0] adrTranslator( 
     input logic [`XLEN-1:0] adrIn);
     begin
-      logic             SvMode, PTE_R, PTE_X;
-      logic [`XLEN-1:0] SATP, PTE;
-      logic [55:0]      BaseAdr, PAdr;
-      logic [8:0]       VPN [2:0];
-      logic [11:0]      Offset;
       int i;
       // Grab the SATP register from privileged unit
       SATP = dut.hart.priv.csr.SATP_REGW;