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condensed always blocks to avoid race conditions

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kaveh pezeshki 2021-02-24 11:35:28 -08:00
parent 3d82ceffb7
commit 3bb8e0d918
1 changed files with 16 additions and 18 deletions
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34
wally-pipelined/testbench/testbench-busybear.sv
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@ -184,7 +184,11 @@ module testbench_busybear();
assign RAMPC = (PCF - (PCF > 'h2fff ? 'h80000000 : 'h1000)) >> 3; assign RAMPC = (PCF - (PCF > 'h2fff ? 'h80000000 : 'h1000)) >> 3;
logic [63:0] readMask; logic [63:0] readMask;
assign readMask = ((1 << (8*(1 << HSIZE))) - 1) << 8 * HADDR[2:0]; assign readMask = ((1 << (8*(1 << HSIZE))) - 1) << 8 * HADDR[2:0];
logic [`XLEN-1:0] readAdrExpected;
always @(HWDATA or HADDR or HSIZE or HWRITE or dut.hart.MemRWM[1]) begin always @(HWDATA or HADDR or HSIZE or HWRITE or dut.hart.MemRWM[1]) begin
if ((HWRITE || dut.hart.MemRWM[1]) && (HADDR >= 'h80000000 && HADDR <= 'h87FFFFFF)) begin if ((HWRITE || dut.hart.MemRWM[1]) && (HADDR >= 'h80000000 && HADDR <= 'h87FFFFFF)) begin
if (HWRITE) begin if (HWRITE) begin
RAM[RAMAdr] = (RAM[RAMAdr] & (~readMask)) | ((HWDATA << 8 * HADDR[2:0]) & readMask); // aligns write data for correct subword size RAM[RAMAdr] = (RAM[RAMAdr] & (~readMask)) | ((HWDATA << 8 * HADDR[2:0]) & readMask); // aligns write data for correct subword size
@ -192,14 +196,7 @@ module testbench_busybear();
readRAM = RAM[RAMAdr] & readMask; readRAM = RAM[RAMAdr] & readMask;
end end
end end
end
always @(PCF) begin
if (PCF >= 'h80000000 && PCF <= 'h87FFFFFF) begin
readPC = RAM[RAMPC] >> PCF[2] * 32;
end
end
// there's almost certianly a better way than just copying this, but its simple enough for now:
always @(HWDATA or HADDR or HSIZE or HWRITE or dut.hart.MemRWM[1]) begin
if ((HWRITE || dut.hart.MemRWM[1]) && (HADDR >= 'h1000 && HADDR <= 'h2FFF)) begin if ((HWRITE || dut.hart.MemRWM[1]) && (HADDR >= 'h1000 && HADDR <= 'h2FFF)) begin
if (HWRITE) begin if (HWRITE) begin
bootram[RAMAdr] = (bootram[RAMAdr] & (~readMask)) | ((HWDATA << 8 * HADDR[2:0]) & readMask); bootram[RAMAdr] = (bootram[RAMAdr] & (~readMask)) | ((HWDATA << 8 * HADDR[2:0]) & readMask);
@ -207,17 +204,7 @@ module testbench_busybear();
readRAM = bootram[RAMAdr] & readMask; readRAM = bootram[RAMAdr] & readMask;
end end
end end
end
always @(PCF) begin
$write(""); // I know this does nothing, the first instruction doesn't load for me without it
if (PCF >= 'h1000 && PCF <= 'h2FFF) begin
readPC = bootram[RAMPC] >> PCF[2] * 32;
end
end
logic [`XLEN-1:0] readAdrExpected;
// this might need to change
always @(dut.hart.MemRWM[1] or HADDR) begin
if (dut.hart.MemRWM[1]) begin if (dut.hart.MemRWM[1]) begin
if($feof(data_file_memR)) begin if($feof(data_file_memR)) begin
$display("no more memR data to read"); $display("no more memR data to read");
@ -240,6 +227,7 @@ module testbench_busybear();
end end
logic [`XLEN-1:0] writeDataExpected, writeAdrExpected; logic [`XLEN-1:0] writeDataExpected, writeAdrExpected;
// this might need to change // this might need to change
always @(HWDATA or HADDR or HSIZE or HWRITE) begin always @(HWDATA or HADDR or HSIZE or HWRITE) begin
#1; #1;
@ -372,6 +360,16 @@ module testbench_busybear();
instrs = 0; instrs = 0;
end end
always @(PCF) begin always @(PCF) begin
if (PCF >= 'h80000000 && PCF <= 'h87FFFFFF) begin
readPC = RAM[RAMPC] >> PCF[2] * 32;
end
//$write(""); // I know this does nothing, the first instruction doesn't load for me without it
if (PCF >= 'h1000 && PCF <= 'h2FFF) begin
readPC = bootram[RAMPC] >> PCF[2] * 32;
end
lastInstrF = InstrF; lastInstrF = InstrF;
lastPC <= PCF; lastPC <= PCF;
lastPC2 <= lastPC; lastPC2 <= lastPC;