Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

hazard was not a straight forward merge.  I changed the way the LSU and IFU generate IFUStallF and LSUStallM.  They need to be suppressed by TrapM now.

pipelined/src/fpu/fdivsqrt/fdivsqrt.sv

@@ -74,7 +74,7 @@ module fdivsqrt(
   fdivsqrtfsm fdivsqrtfsm(
     .clk, .reset, .FmtE, .XsE, .SqrtE, 
     .DivBusy, .DivStartE,.StallE, .StallM, .DivDone, .XZeroE, .YZeroE, 
-    .XNaNE, .YNaNE,
+    .XNaNE, .YNaNE, .MDUE, .n,
     .XInfE, .YInfE, .WZero, .SpecialCaseM);
   fdivsqrtiter fdivsqrtiter(
     .clk, .Firstun, .D, .FirstU, .FirstUM, .FirstC, .SqrtE, .SqrtM, 

pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv

@@ -42,7 +42,9 @@ module fdivsqrtfsm(
   input  logic SqrtE,
   input  logic StallE,
   input  logic StallM,
-  input logic WZero,
+  input  logic WZero,
+  input  logic MDUE,
+  input  logic [`DIVBLEN:0] n,
   output logic DivDone,
   output logic DivBusy,
   output logic SpecialCaseM
@@ -93,7 +95,7 @@ module fdivsqrtfsm(
   always_comb begin 
     if (SqrtE) fbits = Nf + 2 + 2; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2
     else       fbits = Nf + 2 + `LOGR; // Nf + two fractional bits for round/guard + integer bits - try this when placing results in msbs
-    cycles =  (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES);
+    cycles =  MDUE ? n : (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES);
   end 
 
   /* verilator lint_on WIDTH */
@@ -118,6 +120,7 @@ module fdivsqrtfsm(
       end 
   end
 
+  // *** start logic is presently in fctl.  Make it look more like integer division start logic
   assign DivDone = (state == DONE) | (WZero & (state == BUSY));
   assign DivBusy = (state == BUSY & ~DivDone);
 

pipelined/src/hazard/hazard.sv

@@ -70,7 +70,11 @@ module hazard(
   // WFI terminates if any enabled interrupt is pending, even if global interrupts are disabled.  It could also terminate with TW trap
 //  assign StallMCause = (wfiM & (~TrapM & ~IntPendingM)); // | FDivBusyE;  
   assign StallMCause = ((wfiM) & (~TrapM & ~IntPendingM));  //*** Ross: should FDivBusyE trigger StallECause rather than StallMCause similar to DivBusyE?
+  // *** ross: my changes to cache and lsu need to disable ifu/lsu stalls on a Trap.
   assign StallWCause = ((IFUStallF | LSUStallM) & ~TrapM) | (FDivBusyE & ~TrapM & ~IntPendingM);
+  // head version
+  // assign StallWCause = LSUStallM | IFUStallF  | (FDivBusyE & ~TrapM & ~IntPendingM); // *** FDivBusyE should look like DivBusyE  
+
 
   assign #1 StallF = StallFCause | StallD;
   assign #1 StallD = StallDCause | StallE;

pipelined/src/mmu/hptw.sv

@@ -104,14 +104,14 @@ module hptw (
 	assign TLBMiss = (DTLBMissOrDAFaultM | ITLBMissOrDAFaultF);
 
 	// Determine which address to translate
-	assign TranslationVAdr = DTLBWalk ? IEUAdrExtM[`XLEN-1:0] : PCF;
+	mux2 #(`XLEN) vadrmux(PCF, IEUAdrExtM[`XLEN-1:0], DTLBWalk, TranslationVAdr);
+	//assign TranslationVAdr = DTLBWalk ? IEUAdrExtM[`XLEN-1:0] : PCF;
 	assign CurrentPPN = PTE[`PPN_BITS+9:10];
 
 	// State flops
 	flopenr #(1) TLBMissMReg(clk, reset, StartWalk, DTLBMissOrDAFaultM, DTLBWalk); // when walk begins, record whether it was for DTLB (or record 0 for ITLB)
-	assign PRegEn = HPTWRW[1] & ~DCacheStallM;
+	assign PRegEn = HPTWRW[1] & ~DCacheStallM | UpdatePTE;
-  
+	flopenr #(`XLEN) PTEReg(clk, reset, PRegEn, NextPTE, PTE); // Capture page table entry from data cache
-	flopenr #(`XLEN) PTEReg(clk, reset, PRegEn | UpdatePTE, NextPTE, PTE); // Capture page table entry from data cache
 
     
 	// Assign PTE descriptors common across all XLEN values
@@ -287,11 +287,8 @@ module hptw (
   assign CPUBusy = StallW & ~SelHPTW;
 
   // multiplex the outputs to LSU
-  if(`XLEN+2-`PA_BITS > 0) begin  // *** replace with XLEN=32
+  if(`XLEN == 64) assign HPTWAdrExt = {{(`XLEN+2-`PA_BITS){1'b0}}, HPTWAdr}; // extend to 66 bits
-    logic [(`XLEN+2-`PA_BITS)-1:0] zeros;
+  else            assign HPTWAdrExt = HPTWAdr;
-    assign zeros = '0;
-    assign HPTWAdrExt = {zeros, HPTWAdr};
-  end else assign HPTWAdrExt = HPTWAdr;
   mux2 #(2) rwmux(MemRWM, HPTWRW, SelHPTW, PreLSURWM);
   mux2 #(3) sizemux(Funct3M, HPTWSize, SelHPTW, LSUFunct3M);
   mux2 #(7) funct7mux(Funct7M, 7'b0, SelHPTW, LSUFunct7M);