From ff410cd849f3f1374a53b6c8a511e97d877d0cd5 Mon Sep 17 00:00:00 2001 From: cturek Date: Fri, 11 Nov 2022 00:23:25 +0000 Subject: [PATCH 1/3] Added integer step counter to fsm --- pipelined/src/fpu/fdivsqrt/fdivsqrt.sv | 2 +- pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv | 6 ++++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv index 3f9c7e8a..65ea6cc5 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv @@ -74,7 +74,7 @@ module fdivsqrt( fdivsqrtfsm fdivsqrtfsm( .clk, .reset, .FmtE, .XsE, .SqrtE, .DivBusy, .DivStartE,.StallE, .StallM, .DivDone, .XZeroE, .YZeroE, - .XNaNE, .YNaNE, + .XNaNE, .YNaNE, .MDUE, .n, .XInfE, .YInfE, .WZero, .SpecialCaseM); fdivsqrtiter fdivsqrtiter( .clk, .Firstun, .D, .FirstU, .FirstUM, .FirstC, .SqrtE, .SqrtM, diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv index 8dc188c6..94a19ed3 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv @@ -42,7 +42,9 @@ module fdivsqrtfsm( input logic SqrtE, input logic StallE, input logic StallM, - input logic WZero, + input logic WZero, + input logic MDUE, + input logic [`DIVBLEN:0] n, output logic DivDone, output logic DivBusy, output logic SpecialCaseM @@ -93,7 +95,7 @@ module fdivsqrtfsm( always_comb begin if (SqrtE) fbits = Nf + 2 + 2; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2 else fbits = Nf + 2 + `LOGR; // Nf + two fractional bits for round/guard + integer bits - try this when placing results in msbs - cycles = (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES); + cycles = MDUE ? n : (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES); end /* verilator lint_on WIDTH */ From 0502b8ea4d8cb489f3bf7b0723cfa12ec16af6d9 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 13 Nov 2022 04:17:37 -0800 Subject: [PATCH 2/3] Comments about division hazards --- pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv | 1 + pipelined/src/hazard/hazard.sv | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv index 8dc188c6..c64dbc87 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv @@ -118,6 +118,7 @@ module fdivsqrtfsm( end end + // *** start logic is presently in fctl. Make it look more like integer division start logic assign DivDone = (state == DONE) | (WZero & (state == BUSY)); assign DivBusy = (state == BUSY & ~DivDone); diff --git a/pipelined/src/hazard/hazard.sv b/pipelined/src/hazard/hazard.sv index 0ca3c5bc..4eba6700 100644 --- a/pipelined/src/hazard/hazard.sv +++ b/pipelined/src/hazard/hazard.sv @@ -70,7 +70,7 @@ module hazard( // WFI terminates if any enabled interrupt is pending, even if global interrupts are disabled. It could also terminate with TW trap // assign StallMCause = (wfiM & (~TrapM & ~IntPendingM)); // | FDivBusyE; assign StallMCause = ((wfiM) & (~TrapM & ~IntPendingM)); //*** Ross: should FDivBusyE trigger StallECause rather than StallMCause similar to DivBusyE? - assign StallWCause = LSUStallM | IFUStallF | (FDivBusyE & ~TrapM & ~IntPendingM); + assign StallWCause = LSUStallM | IFUStallF | (FDivBusyE & ~TrapM & ~IntPendingM); // *** FDivBusyE should look like DivBusyE in execute stage assign #1 StallF = StallFCause | StallD; assign #1 StallD = StallDCause | StallE; From 157f816cd3de803c7a2ba3efe6e9375106ebaacd Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 13 Nov 2022 04:23:23 -0800 Subject: [PATCH 3/3] HPTW cleanup --- pipelined/src/mmu/hptw.sv | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/pipelined/src/mmu/hptw.sv b/pipelined/src/mmu/hptw.sv index f348d1fd..746c7d58 100644 --- a/pipelined/src/mmu/hptw.sv +++ b/pipelined/src/mmu/hptw.sv @@ -104,14 +104,15 @@ module hptw ( assign TLBMiss = (DTLBMissOrDAFaultNoTrapM | ITLBMissOrDAFaultNoTrapF); // Determine which address to translate - assign TranslationVAdr = DTLBWalk ? IEUAdrExtM[`XLEN-1:0] : PCF; + mux2 #(`XLEN) vadrmux(PCF, IEUAdrExtM[`XLEN-1:0], DTLBWalk, TranslationVAdr); + //assign TranslationVAdr = DTLBWalk ? IEUAdrExtM[`XLEN-1:0] : PCF; assign CurrentPPN = PTE[`PPN_BITS+9:10]; // State flops - flopenr #(1) TLBMissMReg(clk, reset, StartWalk, DTLBMissOrDAFaultNoTrapM, DTLBWalk); // when walk begins, record whether it was for DTLB (or record 0 for ITLB) - assign PRegEn = HPTWRW[1] & ~DCacheStallM; - - flopenr #(`XLEN) PTEReg(clk, reset, PRegEn | UpdatePTE, NextPTE, PTE); // Capture page table entry from data cache + assign PRegEn = HPTWRW[1] & ~DCacheStallM | UpdatePTE; + flopenr #(1) TLBMissMReg(clk, reset, StartWalk, DTLBMissOrDAFaultNoTrapM, DTLBWalk); // when walk begins, record whether it was for DTLB (or record 0 for ITLB) + + flopenr #(`XLEN) PTEReg(clk, reset, PRegEn, NextPTE, PTE); // Capture page table entry from data cache // Assign PTE descriptors common across all XLEN values @@ -282,11 +283,8 @@ module hptw ( assign CPUBusy = StallW & ~SelHPTW; // multiplex the outputs to LSU - if(`XLEN+2-`PA_BITS > 0) begin // *** replace with XLEN=32 - logic [(`XLEN+2-`PA_BITS)-1:0] zeros; - assign zeros = '0; - assign HPTWAdrExt = {zeros, HPTWAdr}; - end else assign HPTWAdrExt = HPTWAdr; + if(`XLEN == 64) assign HPTWAdrExt = {{(`XLEN+2-`PA_BITS){1'b0}}, HPTWAdr}; // extend to 66 bits + else assign HPTWAdrExt = HPTWAdr; mux2 #(2) rwmux(MemRWM, HPTWRW, SelHPTW, PreLSURWM); mux2 #(3) sizemux(Funct3M, HPTWSize, SelHPTW, LSUFunct3M); mux2 #(7) funct7mux(Funct7M, 7'b0, SelHPTW, LSUFunct7M);