From cd58a388e4e26824bbabde85c9d09ce5d72091ae Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 18 Oct 2021 16:56:08 -0500 Subject: [PATCH] fixed issues with dc shell not liking modules with parameters without default values. --- wally-pipelined/src/cache/cachereplacementpolicy.sv | 2 +- wally-pipelined/src/cache/cacheway.sv | 13 ++++++++++++- wally-pipelined/src/mmu/tlbramline.sv | 4 ++-- 3 files changed, 15 insertions(+), 4 deletions(-) diff --git a/wally-pipelined/src/cache/cachereplacementpolicy.sv b/wally-pipelined/src/cache/cachereplacementpolicy.sv index 0e508ca1..01d225b1 100644 --- a/wally-pipelined/src/cache/cachereplacementpolicy.sv +++ b/wally-pipelined/src/cache/cachereplacementpolicy.sv @@ -25,7 +25,7 @@ `include "wally-config.vh" module cachereplacementpolicy - #(NUMWAYS, INDEXLEN, OFFSETLEN, NUMLINES) + #(parameter NUMWAYS = 4, INDEXLEN = 9, OFFSETLEN = 5, NUMLINES = 128) (input logic clk, reset, input logic [NUMWAYS-1:0] WayHit, output logic [NUMWAYS-1:0] VictimWay, diff --git a/wally-pipelined/src/cache/cacheway.sv b/wally-pipelined/src/cache/cacheway.sv index 5a7c3d9e..ad6b980d 100644 --- a/wally-pipelined/src/cache/cacheway.sv +++ b/wally-pipelined/src/cache/cacheway.sv @@ -26,7 +26,7 @@ `include "wally-config.vh" module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26, - parameter OFFSETLEN, parameter INDEXLEN, parameter DIRTY_BITS = 1) + parameter OFFSETLEN = 5, parameter INDEXLEN = 9, parameter DIRTY_BITS = 1) (input logic clk, input logic reset, @@ -109,6 +109,9 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26, ValidBits <= {NUMLINES{1'b0}}; else if (SetValid & (WriteEnable | VDWriteEnable)) ValidBits[WAdr] <= 1'b1; else if (ClearValid & (WriteEnable | VDWriteEnable)) ValidBits[WAdr] <= 1'b0; + end + + always_ff @(posedge clk) begin Valid <= ValidBits[RAdr]; end @@ -119,6 +122,14 @@ module cacheway #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26, DirtyBits <= {NUMLINES{1'b0}}; else if (SetDirty & (WriteEnable | VDWriteEnable)) DirtyBits[WAdr] <= 1'b1; else if (ClearDirty & (WriteEnable | VDWriteEnable)) DirtyBits[WAdr] <= 1'b0; + end + end + endgenerate + + // Since this is always updated on a clock edge we cannot include reset. + generate + if(DIRTY_BITS) begin + always_ff @(posedge clk) begin Dirty <= DirtyBits[RAdr]; end end else begin diff --git a/wally-pipelined/src/mmu/tlbramline.sv b/wally-pipelined/src/mmu/tlbramline.sv index d6d2523c..98a954f8 100644 --- a/wally-pipelined/src/mmu/tlbramline.sv +++ b/wally-pipelined/src/mmu/tlbramline.sv @@ -25,7 +25,7 @@ `include "wally-config.vh" -module tlbramline #(parameter WIDTH) +module tlbramline #(parameter WIDTH = 22) (input logic clk, reset, input logic re, we, input logic [WIDTH-1:0] d, @@ -37,4 +37,4 @@ module tlbramline #(parameter WIDTH) flopenr #(WIDTH) pteflop(clk, reset, we, d, line); assign q = re ? line : 0; assign PTE_G = line[5]; // send global bit to CAM as part of ASID matching -endmodule \ No newline at end of file +endmodule