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Minor simplification of cacheway way selection muxes.

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This commit is contained in:
Ross Thompson 2022-12-09 16:42:05 -06:00
parent 033f844d09
commit 38adcb5b17
2 changed files with 16 additions and 3 deletions
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17
pipelined/src/cache/cacheway.sv vendored
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@ -77,9 +77,22 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
logic SetDirtyWay;
logic ClearDirtyWay;
logic SelectedWay;
logic SelWriteback;
logic SelData;
logic FlushWayEn, VictimWayEn;
assign FlushWayEn = FlushWay & SelFlush;
assign VictimWayEn = VictimWay & SelEvict;
assign SelWriteback = SelFlush | SetValid | SelEvict;
//assign SelWriteback = FlushWay | SetValid | SelEvict;
mux2 #(1) seltagmux(VictimWay, FlushWay, SelFlush, SelTag);
mux2 #(1) selectedwaymux(HitWay, SelTag, SelFlush | SetValid | SelEvict, SelectedWay);
//assign SelTag = VictimWay | FlushWay;
assign SelData = HitWay | FlushWayEn | VictimWayEn;
mux2 #(1) selectedwaymux(HitWay, SelTag, SelWriteback , SelectedWay);
/////////////////////////////////////////////////////////////////////////////////////////////
// Write Enable demux
@ -133,7 +146,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
end
// AND portion of distributed read multiplexers
assign ReadDataLineWay = SelectedWay ? ReadDataLine : '0; // AND part of AO mux.
assign ReadDataLineWay = SelData ? ReadDataLine : '0; // AND part of AO mux.
/////////////////////////////////////////////////////////////////////////////////////////////
// Valid Bits