Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

fpga/constraints/debug2.xdc

@@ -562,9 +562,9 @@ connect_debug_port u_ila_0/probe120 [get_nets [list {wallypipelinedsoc/core/lsu/
 
 
 create_debug_port u_ila_0 probe
-set_property port_width 56 [get_debug_ports u_ila_0/probe121]
+set_property port_width 64 [get_debug_ports u_ila_0/probe121]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe121]
-connect_debug_port u_ila_0/probe121 [get_nets [list {wallypipelinedsoc/core/lsu/IEUAdrM[0]} {wallypipelinedsoc/core/lsu/IEUAdrM[1]} {wallypipelinedsoc/core/lsu/IEUAdrM[2]} {wallypipelinedsoc/core/lsu/IEUAdrM[3]} {wallypipelinedsoc/core/lsu/IEUAdrM[4]} {wallypipelinedsoc/core/lsu/IEUAdrM[5]} {wallypipelinedsoc/core/lsu/IEUAdrM[6]} {wallypipelinedsoc/core/lsu/IEUAdrM[7]} {wallypipelinedsoc/core/lsu/IEUAdrM[8]} {wallypipelinedsoc/core/lsu/IEUAdrM[9]} {wallypipelinedsoc/core/lsu/IEUAdrM[10]} {wallypipelinedsoc/core/lsu/IEUAdrM[11]} {wallypipelinedsoc/core/lsu/IEUAdrM[12]} {wallypipelinedsoc/core/lsu/IEUAdrM[13]} {wallypipelinedsoc/core/lsu/IEUAdrM[14]} {wallypipelinedsoc/core/lsu/IEUAdrM[15]} {wallypipelinedsoc/core/lsu/IEUAdrM[16]} {wallypipelinedsoc/core/lsu/IEUAdrM[17]} {wallypipelinedsoc/core/lsu/IEUAdrM[18]} {wallypipelinedsoc/core/lsu/IEUAdrM[19]} {wallypipelinedsoc/core/lsu/IEUAdrM[20]} {wallypipelinedsoc/core/lsu/IEUAdrM[21]} {wallypipelinedsoc/core/lsu/IEUAdrM[22]} {wallypipelinedsoc/core/lsu/IEUAdrM[23]} {wallypipelinedsoc/core/lsu/IEUAdrM[24]} {wallypipelinedsoc/core/lsu/IEUAdrM[25]} {wallypipelinedsoc/core/lsu/IEUAdrM[26]} {wallypipelinedsoc/core/lsu/IEUAdrM[27]} {wallypipelinedsoc/core/lsu/IEUAdrM[28]} {wallypipelinedsoc/core/lsu/IEUAdrM[29]} {wallypipelinedsoc/core/lsu/IEUAdrM[30]} {wallypipelinedsoc/core/lsu/IEUAdrM[31]} {wallypipelinedsoc/core/lsu/IEUAdrM[32]} {wallypipelinedsoc/core/lsu/IEUAdrM[33]} {wallypipelinedsoc/core/lsu/IEUAdrM[34]} {wallypipelinedsoc/core/lsu/IEUAdrM[35]} {wallypipelinedsoc/core/lsu/IEUAdrM[36]} {wallypipelinedsoc/core/lsu/IEUAdrM[37]} {wallypipelinedsoc/core/lsu/IEUAdrM[38]} {wallypipelinedsoc/core/lsu/IEUAdrM[39]} {wallypipelinedsoc/core/lsu/IEUAdrM[40]} {wallypipelinedsoc/core/lsu/IEUAdrM[41]} {wallypipelinedsoc/core/lsu/IEUAdrM[42]} {wallypipelinedsoc/core/lsu/IEUAdrM[43]} {wallypipelinedsoc/core/lsu/IEUAdrM[44]} {wallypipelinedsoc/core/lsu/IEUAdrM[45]} {wallypipelinedsoc/core/lsu/IEUAdrM[46]} {wallypipelinedsoc/core/lsu/IEUAdrM[47]} {wallypipelinedsoc/core/lsu/IEUAdrM[48]} {wallypipelinedsoc/core/lsu/IEUAdrM[49]} {wallypipelinedsoc/core/lsu/IEUAdrM[50]} {wallypipelinedsoc/core/lsu/IEUAdrM[51]} {wallypipelinedsoc/core/lsu/IEUAdrM[52]} {wallypipelinedsoc/core/lsu/IEUAdrM[53]} {wallypipelinedsoc/core/lsu/IEUAdrM[54]} {wallypipelinedsoc/core/lsu/IEUAdrM[55]} ]]
+connect_debug_port u_ila_0/probe121 [get_nets [list {wallypipelinedsoc/core/SrcAM[0]} {wallypipelinedsoc/core/SrcAM[1]} {wallypipelinedsoc/core/SrcAM[2]} {wallypipelinedsoc/core/SrcAM[3]} {wallypipelinedsoc/core/SrcAM[4]} {wallypipelinedsoc/core/SrcAM[5]} {wallypipelinedsoc/core/SrcAM[6]} {wallypipelinedsoc/core/SrcAM[7]} {wallypipelinedsoc/core/SrcAM[8]} {wallypipelinedsoc/core/SrcAM[9]} {wallypipelinedsoc/core/SrcAM[10]} {wallypipelinedsoc/core/SrcAM[11]} {wallypipelinedsoc/core/SrcAM[12]} {wallypipelinedsoc/core/SrcAM[13]} {wallypipelinedsoc/core/SrcAM[14]} {wallypipelinedsoc/core/SrcAM[15]} {wallypipelinedsoc/core/SrcAM[16]} {wallypipelinedsoc/core/SrcAM[17]} {wallypipelinedsoc/core/SrcAM[18]} {wallypipelinedsoc/core/SrcAM[19]} {wallypipelinedsoc/core/SrcAM[20]} {wallypipelinedsoc/core/SrcAM[21]} {wallypipelinedsoc/core/SrcAM[22]} {wallypipelinedsoc/core/SrcAM[23]} {wallypipelinedsoc/core/SrcAM[24]} {wallypipelinedsoc/core/SrcAM[25]} {wallypipelinedsoc/core/SrcAM[26]} {wallypipelinedsoc/core/SrcAM[27]} {wallypipelinedsoc/core/SrcAM[28]} {wallypipelinedsoc/core/SrcAM[29]} {wallypipelinedsoc/core/SrcAM[30]} {wallypipelinedsoc/core/SrcAM[31]} {wallypipelinedsoc/core/SrcAM[32]} {wallypipelinedsoc/core/SrcAM[33]} {wallypipelinedsoc/core/SrcAM[34]} {wallypipelinedsoc/core/SrcAM[35]} {wallypipelinedsoc/core/SrcAM[36]} {wallypipelinedsoc/core/SrcAM[37]} {wallypipelinedsoc/core/SrcAM[38]} {wallypipelinedsoc/core/SrcAM[39]} {wallypipelinedsoc/core/SrcAM[40]} {wallypipelinedsoc/core/SrcAM[41]} {wallypipelinedsoc/core/SrcAM[42]} {wallypipelinedsoc/core/SrcAM[43]} {wallypipelinedsoc/core/SrcAM[44]} {wallypipelinedsoc/core/SrcAM[45]} {wallypipelinedsoc/core/SrcAM[46]} {wallypipelinedsoc/core/SrcAM[47]} {wallypipelinedsoc/core/SrcAM[48]} {wallypipelinedsoc/core/SrcAM[49]} {wallypipelinedsoc/core/SrcAM[50]} {wallypipelinedsoc/core/SrcAM[51]} {wallypipelinedsoc/core/SrcAM[52]} {wallypipelinedsoc/core/SrcAM[53]} {wallypipelinedsoc/core/SrcAM[54]} {wallypipelinedsoc/core/SrcAM[55]} {wallypipelinedsoc/core/SrcAM[56]} {wallypipelinedsoc/core/SrcAM[57]} {wallypipelinedsoc/core/SrcAM[58]} {wallypipelinedsoc/core/SrcAM[59]} {wallypipelinedsoc/core/SrcAM[60]} {wallypipelinedsoc/core/SrcAM[61]} {wallypipelinedsoc/core/SrcAM[62]} {wallypipelinedsoc/core/SrcAM[63]}]]
 
 
 create_debug_port u_ila_0 probe
@@ -599,18 +599,18 @@ connect_debug_port u_ila_0/probe126 [get_nets [list {wallypipelinedsoc/core/lsu/
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe127]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe127]
-connect_debug_port u_ila_0/probe127 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[63]} ]]
+connect_debug_port u_ila_0/probe127 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[0]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[1]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[2]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[3]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[4]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[5]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[6]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[7]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[8]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[9]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[10]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[11]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[12]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[13]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[14]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[15]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[16]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[17]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[18]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[19]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[20]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[21]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[22]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[23]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[24]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[25]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[26]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[27]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[28]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[29]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[30]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[31]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[32]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[33]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[34]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[35]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[36]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[37]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[38]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[39]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[40]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[41]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[42]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[43]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[44]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[45]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[46]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[47]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[48]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[49]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[50]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[51]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[52]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[53]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[54]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[55]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[56]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[57]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[58]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[59]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[60]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[61]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[62]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[63]} ]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe128]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe128]
-connect_debug_port u_ila_0/probe128 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[63]} ]]
+connect_debug_port u_ila_0/probe128 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[0]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[1]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[2]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[3]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[4]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[5]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[6]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[7]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[8]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[9]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[10]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[11]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[12]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[13]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[14]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[15]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[16]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[17]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[18]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[19]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[20]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[21]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[22]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[23]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[24]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[25]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[26]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[27]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[28]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[29]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[30]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[31]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[32]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[33]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[34]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[35]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[36]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[37]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[38]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[39]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[40]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[41]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[42]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[43]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[44]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[45]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[46]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[47]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[48]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[49]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[50]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[51]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[52]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[53]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[54]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[55]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[56]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[57]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[58]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[59]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[60]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[61]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[62]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[63]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe129]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe129]
-connect_debug_port u_ila_0/probe129 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[63]} ]]
+connect_debug_port u_ila_0/probe129 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[0]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[1]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[2]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[3]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[4]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[5]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[6]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[7]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[8]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[9]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[10]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[11]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[12]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[13]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[14]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[15]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[16]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[17]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[18]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[19]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[20]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[21]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[22]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[23]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[24]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[25]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[26]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[27]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[28]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[29]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[30]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[31]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[32]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[33]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[34]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[35]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[36]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[37]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[38]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[39]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[40]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[41]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[42]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[43]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[44]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[45]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[46]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[47]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[48]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[49]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[50]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[51]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[52]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[53]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[54]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[55]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[56]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[57]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[58]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[59]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[60]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[61]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[62]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[63]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe130]
@@ -651,3 +651,70 @@ create_debug_port u_ila_0 probe
 set_property port_width 12 [get_debug_ports u_ila_0/probe137]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe137]
 connect_debug_port u_ila_0/probe137 [get_nets [list {wallypipelinedsoc/uncore/plic.plic/intPending[1]} {wallypipelinedsoc/uncore/plic.plic/intPending[2]} {wallypipelinedsoc/uncore/plic.plic/intPending[3]} {wallypipelinedsoc/uncore/plic.plic/intPending[4]} {wallypipelinedsoc/uncore/plic.plic/intPending[5]} {wallypipelinedsoc/uncore/plic.plic/intPending[6]} {wallypipelinedsoc/uncore/plic.plic/intPending[7]} {wallypipelinedsoc/uncore/plic.plic/intPending[8]} {wallypipelinedsoc/uncore/plic.plic/intPending[9]} {wallypipelinedsoc/uncore/plic.plic/intPending[10]} {wallypipelinedsoc/uncore/plic.plic/intPending[11]} {wallypipelinedsoc/uncore/plic.plic/intPending[12]}]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 12 [get_debug_ports u_ila_0/probe138]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe138]
+connect_debug_port u_ila_0/probe138 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[0]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[1]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[2]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[3]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[4]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[5]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[6]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[7]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[8]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[9]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[10]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[11]}]]
+
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe139]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe139]
+connect_debug_port u_ila_0/probe139 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/MExtIntM}]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe140]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe140]
+connect_debug_port u_ila_0/probe140 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/SExtIntM} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe141]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe141]
+connect_debug_port u_ila_0/probe141 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/TimerIntM} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe142]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe142]
+connect_debug_port u_ila_0/probe142 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/SwIntM} ]]
+
+
+create_debug_port u_ila_0 probe
+set_property port_width 70 [get_debug_ports u_ila_0/probe143]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe143]
+connect_debug_port u_ila_0/probe143 [get_nets [list {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][10]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 3 [get_debug_ports u_ila_0/probe144]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe144]
+connect_debug_port u_ila_0/probe144 [get_nets [list {wallypipelinedsoc/uncore/plic.plic/intPriority[10][0]} {wallypipelinedsoc/uncore/plic.plic/intPriority[10][1]} {wallypipelinedsoc/uncore/plic.plic/intPriority[10][2]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 10 [get_debug_ports u_ila_0/probe145]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe145]
+connect_debug_port u_ila_0/probe145 [get_nets [list {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[1]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[2]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[3]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[4]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[5]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[6]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[7]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[8]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[9]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[10]} ]]
+
+
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe146]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe146]
+connect_debug_port u_ila_0/probe146 [get_nets [list {wallypipelinedsoc/uncore/clint.clint/MTIME[0]} {wallypipelinedsoc/uncore/clint.clint/MTIME[1]} {wallypipelinedsoc/uncore/clint.clint/MTIME[2]} {wallypipelinedsoc/uncore/clint.clint/MTIME[3]} {wallypipelinedsoc/uncore/clint.clint/MTIME[4]} {wallypipelinedsoc/uncore/clint.clint/MTIME[5]} {wallypipelinedsoc/uncore/clint.clint/MTIME[6]} {wallypipelinedsoc/uncore/clint.clint/MTIME[7]} {wallypipelinedsoc/uncore/clint.clint/MTIME[8]} {wallypipelinedsoc/uncore/clint.clint/MTIME[9]} {wallypipelinedsoc/uncore/clint.clint/MTIME[10]} {wallypipelinedsoc/uncore/clint.clint/MTIME[11]} {wallypipelinedsoc/uncore/clint.clint/MTIME[12]} {wallypipelinedsoc/uncore/clint.clint/MTIME[13]} {wallypipelinedsoc/uncore/clint.clint/MTIME[14]} {wallypipelinedsoc/uncore/clint.clint/MTIME[15]} {wallypipelinedsoc/uncore/clint.clint/MTIME[16]} {wallypipelinedsoc/uncore/clint.clint/MTIME[17]} {wallypipelinedsoc/uncore/clint.clint/MTIME[18]} {wallypipelinedsoc/uncore/clint.clint/MTIME[19]} {wallypipelinedsoc/uncore/clint.clint/MTIME[20]} {wallypipelinedsoc/uncore/clint.clint/MTIME[21]} {wallypipelinedsoc/uncore/clint.clint/MTIME[22]} {wallypipelinedsoc/uncore/clint.clint/MTIME[23]} {wallypipelinedsoc/uncore/clint.clint/MTIME[24]} {wallypipelinedsoc/uncore/clint.clint/MTIME[25]} {wallypipelinedsoc/uncore/clint.clint/MTIME[26]} {wallypipelinedsoc/uncore/clint.clint/MTIME[27]} {wallypipelinedsoc/uncore/clint.clint/MTIME[28]} {wallypipelinedsoc/uncore/clint.clint/MTIME[29]} {wallypipelinedsoc/uncore/clint.clint/MTIME[30]} {wallypipelinedsoc/uncore/clint.clint/MTIME[31]} {wallypipelinedsoc/uncore/clint.clint/MTIME[32]} {wallypipelinedsoc/uncore/clint.clint/MTIME[33]} {wallypipelinedsoc/uncore/clint.clint/MTIME[34]} {wallypipelinedsoc/uncore/clint.clint/MTIME[35]} {wallypipelinedsoc/uncore/clint.clint/MTIME[36]} {wallypipelinedsoc/uncore/clint.clint/MTIME[37]} {wallypipelinedsoc/uncore/clint.clint/MTIME[38]} {wallypipelinedsoc/uncore/clint.clint/MTIME[39]} {wallypipelinedsoc/uncore/clint.clint/MTIME[40]} {wallypipelinedsoc/uncore/clint.clint/MTIME[41]} {wallypipelinedsoc/uncore/clint.clint/MTIME[42]} {wallypipelinedsoc/uncore/clint.clint/MTIME[43]} {wallypipelinedsoc/uncore/clint.clint/MTIME[44]} {wallypipelinedsoc/uncore/clint.clint/MTIME[45]} {wallypipelinedsoc/uncore/clint.clint/MTIME[46]} {wallypipelinedsoc/uncore/clint.clint/MTIME[47]} {wallypipelinedsoc/uncore/clint.clint/MTIME[48]} {wallypipelinedsoc/uncore/clint.clint/MTIME[49]} {wallypipelinedsoc/uncore/clint.clint/MTIME[50]} {wallypipelinedsoc/uncore/clint.clint/MTIME[51]} {wallypipelinedsoc/uncore/clint.clint/MTIME[52]} {wallypipelinedsoc/uncore/clint.clint/MTIME[53]} {wallypipelinedsoc/uncore/clint.clint/MTIME[54]} {wallypipelinedsoc/uncore/clint.clint/MTIME[55]} {wallypipelinedsoc/uncore/clint.clint/MTIME[56]} {wallypipelinedsoc/uncore/clint.clint/MTIME[57]} {wallypipelinedsoc/uncore/clint.clint/MTIME[58]} {wallypipelinedsoc/uncore/clint.clint/MTIME[59]} {wallypipelinedsoc/uncore/clint.clint/MTIME[60]} {wallypipelinedsoc/uncore/clint.clint/MTIME[61]} {wallypipelinedsoc/uncore/clint.clint/MTIME[62]} {wallypipelinedsoc/uncore/clint.clint/MTIME[63]} ]]
+
+
+
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe147]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe147]
+connect_debug_port u_ila_0/probe147 [get_nets [list {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[0]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[1]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[2]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[3]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[4]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[5]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[6]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[7]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[8]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[9]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[10]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[11]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[12]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[13]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[14]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[15]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[16]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[17]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[18]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[19]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[20]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[21]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[22]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[23]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[24]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[25]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[26]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[27]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[28]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[29]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[30]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[31]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[32]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[33]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[34]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[35]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[36]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[37]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[38]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[39]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[40]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[41]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[42]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[43]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[44]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[45]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[46]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[47]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[48]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[49]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[50]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[51]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[52]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[53]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[54]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[55]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[56]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[57]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[58]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[59]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[60]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[61]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[62]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[63]} ]]
+
+
+
+create_debug_port u_ila_0 probe
+set_property port_width 12 [get_debug_ports u_ila_0/probe148]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe148]
+connect_debug_port u_ila_0/probe148 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[11]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe149]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe149]
+connect_debug_port u_ila_0/probe149 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[63]} ]]

fpga/generator/wave_config.wcfg

@@ -0,0 +1,495 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="/home/ross/repos/riscv-wally/fpga/generator/WallyFPGA.hw/hw_1/wave/hw_ila_data_1/hw_ila_data_1.wdb" id="1">
+         <top_modules>
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <zoom_setting>
+      <ZoomStartTime time="0fs"></ZoomStartTime>
+      <ZoomEndTime time="16385fs"></ZoomEndTime>
+      <Cursor1Time time="6fs"></Cursor1Time>
+   </zoom_setting>
+   <column_width_setting>
+      <NameColumnWidth column_width="452"></NameColumnWidth>
+      <ValueColumnWidth column_width="145"></ValueColumnWidth>
+   </column_width_setting>
+   <WVObjectSize size="29" />
+   <wave_markers>
+   </wave_markers>
+   <wvobject type="array" fp_name="wallypipelinedsoc/core/PCM">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/PCM[63:0]</obj_property>
+      <obj_property name="ObjectShortName">PCM[63:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="wallypipelinedsoc/core/InstrM">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/InstrM[31:0]</obj_property>
+      <obj_property name="ObjectShortName">InstrM[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="wallypipelinedsoc/core/InstrValidM">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/InstrValidM</obj_property>
+      <obj_property name="ObjectShortName">InstrValidM</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="wallypipelinedsoc/core/TrapM">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/TrapM</obj_property>
+      <obj_property name="ObjectShortName">TrapM</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="group" fp_name="group468">
+      <obj_property name="label">CPU to LSU</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="isExpanded"></obj_property>
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/IEUAdrM">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/IEUAdrM[63:0]</obj_property>
+         <obj_property name="ObjectShortName">IEUAdrM[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/MemRWM">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/MemRWM[1:0]</obj_property>
+         <obj_property name="ObjectShortName">MemRWM[1:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/ReadDataM">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/ReadDataM[63:0]</obj_property>
+         <obj_property name="ObjectShortName">ReadDataM[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/WriteDataM">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/WriteDataM[63:0]</obj_property>
+         <obj_property name="ObjectShortName">WriteDataM[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject type="group" fp_name="group469">
+      <obj_property name="label">xIP</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="isExpanded"></obj_property>
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW_5">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MIP_REGW_5[9:9]</obj_property>
+         <obj_property name="ObjectShortName">MIP_REGW_5[9:9]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/trap/SIP_REGW">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/trap/SIP_REGW[9:9]</obj_property>
+         <obj_property name="ObjectShortName">SIP_REGW[9:9]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject type="group" fp_name="group470">
+      <obj_property name="label">PLIC</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="isExpanded"></obj_property>
+      <wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/requests">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/requests[12:1]</obj_property>
+         <obj_property name="ObjectShortName">requests[12:1]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/intPending">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/intPending[12:1]</obj_property>
+         <obj_property name="ObjectShortName">intPending[12:1]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/intInProgress">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/intInProgress[12:1]</obj_property>
+         <obj_property name="ObjectShortName">intInProgress[12:1]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject type="group" fp_name="group471">
+      <obj_property name="label">interrupts</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="isExpanded"></obj_property>
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW">
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[63:0]</obj_property>
+         <obj_property name="ObjectShortName">MEDELEG_REGW[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW">
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[11:0]</obj_property>
+         <obj_property name="ObjectShortName">MIDELEG_REGW[11:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/trap/MPendingIntsM">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/trap/MPendingIntsM[11:0]</obj_property>
+         <obj_property name="ObjectShortName">MPendingIntsM[11:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/trap/SPendingIntsM[11:0]</obj_property>
+         <obj_property name="ObjectShortName">SPendingIntsM[11:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/InterruptM">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/InterruptM</obj_property>
+         <obj_property name="ObjectShortName">InterruptM</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject type="group" fp_name="group463">
+      <obj_property name="label">LSU to Bus</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="isExpanded"></obj_property>
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/lsu/LSUBusRead">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUBusRead</obj_property>
+         <obj_property name="ObjectShortName">LSUBusRead</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/lsu/LSUBusWrite">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUBusWrite</obj_property>
+         <obj_property name="ObjectShortName">LSUBusWrite</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/LSUBusAdr">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUBusAdr[31:0]</obj_property>
+         <obj_property name="ObjectShortName">LSUBusAdr[31:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/LSUBusSize">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUBusSize[1:0]</obj_property>
+         <obj_property name="ObjectShortName">LSUBusSize[1:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/LSUBusHWDATA">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUBusHWDATA[63:0]</obj_property>
+         <obj_property name="ObjectShortName">LSUBusHWDATA[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/lsu/LSUBusHRDATA">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUBusHRDATA[63:0]</obj_property>
+         <obj_property name="ObjectShortName">LSUBusHRDATA[63:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="wallypipelinedsoc/core/lsu/LSUBusAck">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUBusAck</obj_property>
+         <obj_property name="ObjectShortName">LSUBusAck</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject type="group" fp_name="group488">
+      <obj_property name="label">xIE</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW_1">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW_1[1:1]</obj_property>
+         <obj_property name="ObjectShortName">MIE_REGW_1[1:1]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW_2">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW_2[3:3]</obj_property>
+         <obj_property name="ObjectShortName">MIE_REGW_2[3:3]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW_3">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW_3[5:5]</obj_property>
+         <obj_property name="ObjectShortName">MIE_REGW_3[5:5]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW_4">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW_4[7:7]</obj_property>
+         <obj_property name="ObjectShortName">MIE_REGW_4[7:7]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW_5">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW_5[9:9]</obj_property>
+         <obj_property name="ObjectShortName">MIE_REGW_5[9:9]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MIE_REGW[11:11]</obj_property>
+         <obj_property name="ObjectShortName">MIE_REGW[11:11]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/trap/SIE_REGW">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/trap/SIE_REGW[9:9]</obj_property>
+         <obj_property name="ObjectShortName">SIE_REGW[9:9]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/trap/SIE_REGW_1">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/trap/SIE_REGW_1[1:1]</obj_property>
+         <obj_property name="ObjectShortName">SIE_REGW_1[1:1]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/trap/SIE_REGW_2">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/trap/SIE_REGW_2[5:5]</obj_property>
+         <obj_property name="ObjectShortName">SIE_REGW_2[5:5]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject type="group" fp_name="group487">
+      <obj_property name="label">sdc</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="isExpanded"></obj_property>
+      <wvobject type="logic" fp_name="wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_ERROR_Q">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_ERROR_Q</obj_property>
+         <obj_property name="ObjectShortName">r_DAT_ERROR_Q</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[4:0]</obj_property>
+         <obj_property name="ObjectShortName">r_curr_state[4:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state[3:0]</obj_property>
+         <obj_property name="ObjectShortName">r_curr_state[3:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="array" fp_name="wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state[3:0]</obj_property>
+         <obj_property name="ObjectShortName">r_curr_state[3:0]</obj_property>
+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/i_ERROR_CRC16">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/i_ERROR_CRC16</obj_property>
+         <obj_property name="ObjectShortName">i_ERROR_CRC16</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[11:0]</obj_property>
+      <obj_property name="ObjectShortName">IP_REGW_writeable[11:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/csr/csri/MExtIntM">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csri/MExtIntM</obj_property>
+      <obj_property name="ObjectShortName">MExtIntM</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/csr/csri/SExtIntM">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csri/SExtIntM</obj_property>
+      <obj_property name="ObjectShortName">SExtIntM</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/csr/csri/SwIntM">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csri/SwIntM</obj_property>
+      <obj_property name="ObjectShortName">SwIntM</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/csr/csri/TimerIntM">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csri/TimerIntM</obj_property>
+      <obj_property name="ObjectShortName">TimerIntM</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[63:0]</obj_property>
+      <obj_property name="ObjectShortName">MEDELEG_REGW[63:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[11:0]</obj_property>
+      <obj_property name="ObjectShortName">MIDELEG_REGW[11:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="wallypipelinedsoc/uncore/clint.clint/MTIMECMP">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/uncore/clint.clint/MTIMECMP[63:0]</obj_property>
+      <obj_property name="ObjectShortName">MTIMECMP[63:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="wallypipelinedsoc/uncore/clint.clint/MTIME">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/uncore/clint.clint/MTIME[63:0]</obj_property>
+      <obj_property name="ObjectShortName">MTIME[63:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/intEn[1]__0">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[10:1]</obj_property>
+      <obj_property name="ObjectShortName">intEn[1]__0[10:1]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/intPriority[10]">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/intPriority[10][2:0]</obj_property>
+      <obj_property name="ObjectShortName">intPriority[10][2:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1]">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][10:1]</obj_property>
+      <obj_property name="ObjectShortName">irqMatrix[1][1][10:1]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2]">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][10:1]</obj_property>
+      <obj_property name="ObjectShortName">irqMatrix[1][2][10:1]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3]">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][10:1]</obj_property>
+      <obj_property name="ObjectShortName">irqMatrix[1][3][10:1]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4]">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][10:1]</obj_property>
+      <obj_property name="ObjectShortName">irqMatrix[1][4][10:1]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5]">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][10:1]</obj_property>
+      <obj_property name="ObjectShortName">irqMatrix[1][5][10:1]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6]">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][10:1]</obj_property>
+      <obj_property name="ObjectShortName">irqMatrix[1][6][10:1]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7]">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][10:1]</obj_property>
+      <obj_property name="ObjectShortName">irqMatrix[1][7][10:1]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+</wave_config>

pipelined/config/fpga/wally-config.vh

@@ -42,6 +42,7 @@
 `define ZIFENCEI_SUPPORTED 1
 `define ZICOUNTERS_SUPPORTED 1
 `define COUNTERS 32
+`define DESIGN_COMPILER 0
 
 // Microarchitectural Features
 `define UARCH_PIPELINED 1

pipelined/config/rv32ia/wally-config.vh

@@ -0,0 +1,135 @@
+//////////////////////////////////////////
+// wally-config.vh
+//
+// Written: David_Harris@hmc.edu 4 January 2021
+// Modified: 
+//
+// Purpose: Specify which features are configured
+//          Macros to determine which modes are supported based on MISA
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+// include shared configuration
+`include "wally-shared.vh"
+
+`define FPGA 0
+`define QEMU 0
+`define DESIGN_COMPILER 0
+
+// RV32 or RV64: XLEN = 32 or 64
+`define XLEN 32
+
+// IEEE 754 compliance
+`define IEEE754 0
+
+// IA
+`define MISA (32'h00000100 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0 | 1 << 3 | 1 << 5)
+`define ZICSR_SUPPORTED 1
+`define ZIFENCEI_SUPPORTED 1
+`define COUNTERS 32
+`define ZICOUNTERS_SUPPORTED 1
+
+// Microarchitectural Features
+`define UARCH_PIPELINED 1
+`define UARCH_SUPERSCALR 0
+`define UARCH_SINGLECYCLE 0
+// *** replace with MEM_BUS
+`define DMEM `MEM_CACHE
+`define IMEM `MEM_CACHE
+`define DBUS 1
+`define IBUS 1
+`define VIRTMEM_SUPPORTED 1
+`define VECTORED_INTERRUPTS_SUPPORTED 1 
+
+// TLB configuration.  Entries should be a power of 2
+`define ITLB_ENTRIES 32
+`define DTLB_ENTRIES 32
+
+// Cache configuration.  Sizes should be a power of two
+// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
+`define DCACHE_NUMWAYS 4
+`define DCACHE_WAYSIZEINBYTES 4096
+`define DCACHE_LINELENINBITS 256
+`define ICACHE_NUMWAYS 4
+`define ICACHE_WAYSIZEINBYTES 4096
+`define ICACHE_LINELENINBITS 256
+
+// Integer Divider Configuration
+// DIV_BITSPERCYCLE must be 1, 2, or 4
+`define DIV_BITSPERCYCLE 4
+
+// Legal number of PMP entries are 0, 16, or 64
+`define PMP_ENTRIES 64
+
+// Address space
+`define RESET_VECTOR 32'h80000000
+
+// Peripheral Addresses
+// Peripheral memory space extends from BASE to BASE+RANGE
+// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
+`define BOOTROM_SUPPORTED 1'b1
+`define BOOTROM_BASE   34'h00001000 
+`define BOOTROM_RANGE  34'h00000FFF
+`define RAM_SUPPORTED 1'b1
+`define RAM_BASE       34'h80000000
+`define RAM_RANGE      34'h07FFFFFF
+`define EXT_MEM_SUPPORTED 1'b0
+`define EXT_MEM_BASE       34'h80000000
+`define EXT_MEM_RANGE      34'h07FFFFFF
+`define CLINT_SUPPORTED 1'b0
+`define CLINT_BASE  34'h02000000
+`define CLINT_RANGE 34'h0000FFFF
+`define GPIO_SUPPORTED 1'b0
+`define GPIO_BASE   34'h10060000
+`define GPIO_RANGE  34'h000000FF
+`define UART_SUPPORTED 1'b1
+`define UART_BASE   34'h10000000
+`define UART_RANGE  34'h00000007
+`define PLIC_SUPPORTED 1'b1
+`define PLIC_BASE   34'h0C000000
+`define PLIC_RANGE  34'h03FFFFFF
+`define SDC_SUPPORTED 1'b0
+`define SDC_BASE   34'h00012100
+`define SDC_RANGE  34'h0000001F
+
+// Bus Interface width
+`define AHBW 32
+
+// Test modes
+
+// Tie GPIO outputs back to inputs
+`define GPIO_LOOPBACK_TEST 1
+
+// Hardware configuration
+`define UART_PRESCALE 1
+
+// Interrupt configuration
+`define PLIC_NUM_SRC 10 
+// comment out the following if >=32 sources
+`define PLIC_NUM_SRC_LT_32
+`define PLIC_GPIO_ID 3
+`define PLIC_UART_ID 10
+
+`define TWO_BIT_PRELOAD "../config/rv32ia/twoBitPredictor.txt"
+`define BTB_PRELOAD "../config/rv32ia/BTBPredictor.txt"
+`define BPRED_ENABLED 1
+`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
+`define TESTSBP 0
+
+`define REPLAY 0
+`define HPTW_WRITES_SUPPORTED 0

pipelined/config/rv64ia/wally-config.vh

@@ -0,0 +1,136 @@
+//////////////////////////////////////////
+// wally-config.vh
+//
+// Written: David_Harris@hmc.edu 4 January 2021
+// Modified: 
+//
+// Purpose: Specify which features are configured
+//          Macros to determine which modes are supported based on MISA
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+// include shared configuration
+`include "wally-shared.vh"
+
+`define FPGA 0
+`define QEMU 0
+`define DESIGN_COMPILER 0
+
+// RV32 or RV64: XLEN = 32 or 64
+`define XLEN 64
+
+// IEEE 754 compliance
+`define IEEE754 0
+
+// MISA RISC-V configuration per specification IA
+`define MISA (32'h00000100 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0 | 1 << 3 | 1 << 5)
+`define ZICSR_SUPPORTED 1
+`define ZIFENCEI_SUPPORTED 1
+`define COUNTERS 32
+`define ZICOUNTERS_SUPPORTED 1
+
+/// Microarchitectural Features
+`define UARCH_PIPELINED 1
+`define UARCH_SUPERSCALR 0
+`define UARCH_SINGLECYCLE 0
+`define DMEM `MEM_CACHE
+`define IMEM `MEM_CACHE
+`define DBUS 1
+`define IBUS 1
+`define VIRTMEM_SUPPORTED 1
+`define VECTORED_INTERRUPTS_SUPPORTED 1 
+
+// TLB configuration.  Entries should be a power of 2
+`define ITLB_ENTRIES 32
+`define DTLB_ENTRIES 32
+
+// Cache configuration.  Sizes should be a power of two
+// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
+`define DCACHE_NUMWAYS 4
+`define DCACHE_WAYSIZEINBYTES 4096
+`define DCACHE_LINELENINBITS 256
+`define ICACHE_NUMWAYS 4
+`define ICACHE_WAYSIZEINBYTES 4096
+`define ICACHE_LINELENINBITS 256
+
+// Integer Divider Configuration
+// DIV_BITSPERCYCLE must be 1, 2, or 4
+`define DIV_BITSPERCYCLE 4
+
+// Legal number of PMP entries are 0, 16, or 64
+`define PMP_ENTRIES 64
+
+// Address space
+`define RESET_VECTOR 64'h0000000080000000
+
+// Bus Interface width
+`define AHBW 64
+
+// Peripheral Physiccal Addresses
+// Peripheral memory space extends from BASE to BASE+RANGE
+// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
+
+// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
+`define BOOTROM_SUPPORTED 1'b1
+`define BOOTROM_BASE   56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
+`define BOOTROM_RANGE  56'h00000FFF
+`define RAM_SUPPORTED 1'b1
+`define RAM_BASE       56'h80000000
+`define RAM_RANGE      56'h7FFFFFFF
+`define EXT_MEM_SUPPORTED 1'b0
+`define EXT_MEM_BASE       56'h80000000
+`define EXT_MEM_RANGE      56'h07FFFFFF
+`define CLINT_SUPPORTED 1'b1
+`define CLINT_BASE  56'h02000000
+`define CLINT_RANGE 56'h0000FFFF
+`define GPIO_SUPPORTED 1'b1
+`define GPIO_BASE   56'h10060000
+`define GPIO_RANGE  56'h000000FF
+`define UART_SUPPORTED 1'b1
+`define UART_BASE   56'h10000000
+`define UART_RANGE  56'h00000007
+`define PLIC_SUPPORTED 1'b1
+`define PLIC_BASE   56'h0C000000
+`define PLIC_RANGE  56'h03FFFFFF
+`define SDC_SUPPORTED 1'b0
+`define SDC_BASE   56'h00012100
+`define SDC_RANGE  56'h0000001F
+
+// Test modes
+
+// Tie GPIO outputs back to inputs
+`define GPIO_LOOPBACK_TEST 1
+
+// Hardware configuration
+`define UART_PRESCALE 1
+
+// Interrupt configuration
+`define PLIC_NUM_SRC 10
+// comment out the following if >=32 sources
+`define PLIC_NUM_SRC_LT_32
+`define PLIC_GPIO_ID 3
+`define PLIC_UART_ID 10
+
+`define TWO_BIT_PRELOAD "../config/rv64ia/twoBitPredictor.txt"
+`define BTB_PRELOAD "../config/rv64ia/BTBPredictor.txt"
+`define BPRED_ENABLED 1
+`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
+`define TESTSBP 0
+
+`define REPLAY 0
+`define HPTW_WRITES_SUPPORTED 0

pipelined/regression/regression-wally

@@ -62,7 +62,7 @@ tc = TestCase(
       grepstr="400100000 instructions")
 configs.append(tc)
 
-tests64gc = ["arch64i", "arch64priv", "arch64c",  "arch64m", "arch64d", "imperas64i", "imperas64f", "imperas64d", "imperas64m", "wally64a",  "imperas64c", "wally64priv", "wally64periph"] # , "imperas64mmu" "wally64i", #,  "testsBP64"] 
+tests64gc = ["arch64i", "arch64priv", "arch64c",  "arch64m", "arch64d", "imperas64i", "imperas64f", "imperas64d", "imperas64m", "wally64a",  "imperas64c", "wally64periph"] # , "imperas64mmu" "wally64i", #,  "testsBP64"] 
 for test in tests64gc:
   tc = TestCase(
         name=test,

pipelined/src/privileged/csr.sv

@@ -33,9 +33,8 @@
 `include "wally-config.vh"
 
 module csr #(parameter
-  // Constants
+    MIP = 12'h344,
-  UIP_REGW = 12'b0, // N user-mode exceptions not supported
+    SIP = 12'h144
-  UIE_REGW = 12'b0
   ) (
   input  logic             clk, reset,
   input  logic             FlushE, FlushM, FlushW,
@@ -76,8 +75,11 @@ module csr #(parameter
 );
 
   localparam NOP = 32'h13;
-  logic [`XLEN-1:0] CSRMReadValM, CSRSReadValM, CSRUReadValM, CSRCReadValM, CSRReadValM;
+  logic [`XLEN-1:0] CSRMReadValM, CSRSReadValM, CSRUReadValM, CSRCReadValM;
-  logic [`XLEN-1:0] CSRSrcM, CSRRWM, CSRRSM, CSRRCM, CSRWriteValM;
+(* mark_debug = "true" *)  logic [`XLEN-1:0] CSRReadValM;  
+(* mark_debug = "true" *)  logic [`XLEN-1:0] CSRSrcM;
+  logic [`XLEN-1:0] CSRRWM, CSRRSM, CSRRCM;  
+(* mark_debug = "true" *)  logic [`XLEN-1:0] CSRWriteValM;
  
 (* mark_debug = "true" *)  logic [`XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW;
   logic [31:0]     MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW;
@@ -92,6 +94,8 @@ module csr #(parameter
   //logic [11:0] UIP_REGW, UIE_REGW = 0; // N user-mode exceptions not supported
   logic        IllegalCSRCAccessM, IllegalCSRMAccessM, IllegalCSRSAccessM, IllegalCSRUAccessM, InsufficientCSRPrivilegeM;
   logic IllegalCSRMWriteReadonlyM;
+  logic [`XLEN-1:0] CSRReadVal2M;
+  logic [11:0] IP_REGW_writeable;
   
   logic InstrValidNotFlushedM;
   assign InstrValidNotFlushedM = ~StallW & ~FlushW;
@@ -100,10 +104,15 @@ module csr #(parameter
   always_comb begin
     // Choose either rs1 or uimm[4:0] as source
     CSRSrcM = InstrM[14] ? {{(`XLEN-5){1'b0}}, InstrM[19:15]} : SrcAM;
+
+    // CSR set and clear for MIP/SIP should only touch internal state, not interrupt inputs
+    if (CSRAdrM == MIP | CSRAdrM == SIP) CSRReadVal2M = {{(`XLEN-12){1'b0}}, IP_REGW_writeable};
+    else                                 CSRReadVal2M = CSRReadValM;
+
     // Compute AND/OR modification
     CSRRWM = CSRSrcM;
-    CSRRSM = CSRReadValM | CSRSrcM;
+    CSRRSM = CSRReadVal2M | CSRSrcM;
-    CSRRCM = CSRReadValM & ~CSRSrcM;
+    CSRRCM = CSRReadVal2M & ~CSRSrcM;
     case (InstrM[13:12])
       2'b01:  CSRWriteValM = CSRRWM;
       2'b10:  CSRWriteValM = CSRRSM;
@@ -125,7 +134,7 @@ module csr #(parameter
   csri   csri(.clk, .reset, .InstrValidNotFlushedM, .StallW, 
               .CSRMWriteM, .CSRSWriteM, .CSRWriteValM, .CSRAdrM, 
               .MExtIntM, .SExtIntM, .TimerIntM, .SwIntM,
-              .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .MIDELEG_REGW);
+              .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .MIDELEG_REGW, .IP_REGW_writeable);
   csrsr csrsr(.clk, .reset, .StallW,
               .WriteMSTATUSM, .WriteSSTATUSM, 
               .TrapM, .FRegWriteM, .NextPrivilegeModeM, .PrivilegeModeW,

pipelined/src/privileged/csri.sv

@@ -37,17 +37,17 @@ module csri #(parameter
     SIE = 12'h104,
     SIP = 12'h144
   ) (
-    input  logic             clk, reset, 
+    input logic 			clk, reset, 
-    input  logic             InstrValidNotFlushedM, StallW,
+    input logic 			InstrValidNotFlushedM, StallW,
-    input  logic             CSRMWriteM, CSRSWriteM,
+    input logic 			CSRMWriteM, CSRSWriteM,
-    input  logic [`XLEN-1:0] CSRWriteValM,
+    input logic [`XLEN-1:0] CSRWriteValM,
-    input  logic [11:0]      CSRAdrM,
+    input logic [11:0] 		CSRAdrM,
-    input  logic             MExtIntM, SExtIntM, TimerIntM, SwIntM,
+    (* mark_debug = "true" *)    input logic MExtIntM, SExtIntM, TimerIntM, SwIntM,
-    input  logic [11:0]      MIDELEG_REGW,
+    input logic [11:0] 		MIDELEG_REGW,
-    output logic [11:0]      MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW
+    output logic [11:0] 	MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW, 
+    (* mark_debug = "true" *) output logic [11:0]   IP_REGW_writeable // only SEIP, STIP, SSIP are actually writeable; the rest are hardwired to 0
   );
 
-  logic [11:0]     IP_REGW_writeable; // only SEIP, STIP, SSIP are actually writeable; the rest are hardwired to 0
   logic [11:0]     IP_REGW, IE_REGW;
   logic [11:0]     MIP_WRITE_MASK, SIP_WRITE_MASK, MIE_WRITE_MASK;
   logic            WriteMIPM, WriteMIEM, WriteSIPM, WriteSIEM;

pipelined/src/privileged/csrm.sv

@@ -78,8 +78,8 @@ module csrm #(parameter
     output logic [`XLEN-1:0] CSRMReadValM, MTVEC_REGW,
     (* mark_debug = "true" *)  output logic [`XLEN-1:0] MEPC_REGW,    
     output logic [31:0]      MCOUNTEREN_REGW, MCOUNTINHIBIT_REGW, 
-    output logic [`XLEN-1:0] MEDELEG_REGW,
+(* mark_debug = "true" *)      output logic [`XLEN-1:0] MEDELEG_REGW,
-    output logic [11:0]      MIDELEG_REGW,
+(* mark_debug = "true" *)      output logic [11:0]      MIDELEG_REGW,
     // 64-bit registers in RV64, or two 32-bit registers in RV32
     //output var logic [63:0]      PMPCFG_ARRAY_REGW[`PMP_ENTRIES/8-1:0],
     output 		     var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],

pipelined/src/uncore/clint.sv

@@ -32,25 +32,25 @@
 `include "wally-config.vh"
 
 module clint (
-  input  logic             HCLK, HRESETn, TIMECLK,
+  input logic 			   HCLK, HRESETn, TIMECLK,
-  input  logic             HSELCLINT,
+  input logic 			   HSELCLINT,
-  input  logic [15:0]      HADDR,
+  input logic [15:0] 	   HADDR,
-  input  logic [3:0]       HSIZED,
+  input logic [3:0] 	   HSIZED,
-  input  logic             HWRITE,
+  input logic 			   HWRITE,
-  input  logic [`XLEN-1:0] HWDATA,
+  input logic [`XLEN-1:0]  HWDATA,
-  input  logic             HREADY,
+  input logic 			   HREADY,
-  input  logic [1:0]       HTRANS,
+  input logic [1:0] 	   HTRANS,
   output logic [`XLEN-1:0] HREADCLINT,
-  output logic             HRESPCLINT, HREADYCLINT,
+  output logic 			   HRESPCLINT, HREADYCLINT,
-  output logic [63:0]      MTIME, 
+  (* mark_debug = "true" *) output logic [63:0] MTIME, 
-  output logic             TimerIntM, SwIntM);
+  output logic 			   TimerIntM, SwIntM);
 
   logic        MSIP;
 
   logic [15:0] entry, entryd;
   logic memwrite;
   logic initTrans;
-  logic [63:0] MTIMECMP;
+  (* mark_debug = "true" *)    logic [63:0] MTIMECMP;
   logic [`XLEN/8-1:0] ByteMaskM;
   integer             i;
 

pipelined/src/uncore/plic.sv

@@ -70,9 +70,9 @@ module plic (
   
   // context-dependent signals
   logic [`C-1:0][2:0]       intThreshold;
-  logic [`C-1:0][`N:1]      intEn;
+    (* mark_debug = "true" *)  logic [`C-1:0][`N:1]      intEn;
   logic [`C-1:0][5:0]       intClaim; // ID's are 6 bits if we stay within 63 sources
-  logic [`C-1:0][7:1][`N:1] irqMatrix;
+    (* mark_debug = "true" *)  logic [`C-1:0][7:1][`N:1] irqMatrix;
   logic [`C-1:0][7:1]       priorities_with_irqs;
   logic [`C-1:0][7:1]       max_priority_with_irqs;
   logic [`C-1:0][`N:1]      irqs_at_max_priority;

pipelined/src/wally/wallypipelinedcore.sv

@@ -66,7 +66,7 @@ module wallypipelinedcore (
   logic [1:0]             AtomicE;
   logic [1:0]             AtomicM;
   logic [`XLEN-1:0]     ForwardedSrcAE, ForwardedSrcBE; //, SrcAE, SrcBE;
-  logic [`XLEN-1:0]         SrcAM;
+(* mark_debug = "true" *)  logic [`XLEN-1:0]         SrcAM;
   logic [2:0]             Funct3E;
   //  logic [31:0] InstrF;
   logic [31:0]             InstrD, InstrW;

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefile

@@ -1,3 +1,5 @@
 include ../../Makefile.include
 
+RVTEST_DEFINES += -march=rv$(XLEN)ia # KMG: removed compressed instructions from privileged tests
+
 $(eval $(call compile_template,-march=rv32iac -mabi=ilp32 -Drvtest_mtrap_routine=True -DXLEN=$(XLEN)))

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output

@@ -0,0 +1,990 @@
+00000aaa # Test 5.3.1.4: readback value from writing mie to enable interrupts
+00000001 # mcause from an instruction access fault
+00000000 # mtval of faulting instruction address (0x0)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000002 # mcause from an Illegal instruction
+00000000 # mtval of faulting instruction (0x0)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000003 # mcause from Breakpoint
+800003ec # mtval of breakpoint instruction adress (0x800003ec)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000004 # mcause from load address misaligned
+800003f5 # mtval of misaligned address (0x800003f5)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000005 # mcause from load access
+00000000 # mtval of accessed adress (0x0)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000006 # mcause from store misaligned
+80000411 # mtval of address with misaligned store instr (0x80000410)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000007 # mcause from store access
+00000000 # mtval of accessed address (0x0)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+0000000b # mcause from M mode ecall 
+00000000 # mtval of ecall (*** defined to be zero for now)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000008 # mcause from U mode ecall 
+00000000 # mtval of ecall (*** defined to be zero for now)
+00000080 # masked out mstatus.MPP = 00 (from U mode), mstatus.MPIE = 1, and mstatus.MIE = 0
+00000009 # mcause from S mode ecall 
+00000000 # mtval of ecall (*** defined to be zero for now)
+00000880 # masked out mstatus.MPP = 01 (from S mode), mstatus.MPIE = 1, and mstatus.MIE = 0
+000007ec # value to indicate a vectored interrupts
+80000007 # mcause value from m time interrupt
+00000000 # mtval for mtime interrupt (0x0)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+000007ec # value to indicate a vectored interrupts
+80000001 # mcause value from m soft interrupt
+00000000 # mtval for msoft interrupt (0x0)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+000007ec # value to indicate a vectored interrupts
+8000000b # mcause value from m ext interrupt
+00000000 # mtval for mext interrupt (0x0)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+0000b309 # medeleg after attempted write of all 1's (only some bits are writeable)
+00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
+00000001 # Test 5.3.1.4: mcause from an instruction access fault
+00000000 # mtval of faulting instruction address (0x0)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000002 # mcause from an Illegal instruction
+00000000 # mtval of faulting instruction (0x0)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000003 # mcause from Breakpoint
+800003ec # mtval of breakpoint instruction adress (0x800003ec)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000004 # mcause from load address misaligned
+800003f5 # mtval of misaligned address (0x800003f5)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000005 # mcause from load access
+00000000 # mtval of accessed adress (0x0)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000006 # mcause from store misaligned
+80000411 # mtval of address with misaligned store instr (0x80000410)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000007 # mcause from store access
+00000000 # mtval of accessed address (0x0)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+0000000b # mcause from M mode ecall 
+00000000 # mtval of ecall (*** defined to be zero for now)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+000007ec # value to indicate a vectored interrupts
+80000007 # mcause value from  time interrupt
+00000000 # mtval for mtime interrupt (0x0)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+000007ec # value to indicate a vectored interrupts
+80000001 # mcause value from m soft interrupt
+00000000 # mtval for msoft interrupt (0x0)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+000007ec # value to indicate a vectored interrupts
+0000000b # mcause value from m ext interrupt
+00000000 # mtval for mext interrupt (0x0)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+0000000b # mcause from M mode ecall from test termination
+00000000 # mtval of ecall (*** defined to be zero for now)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef
+deadbeef

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-CSR-permission-s-01.S

@@ -25,7 +25,7 @@
 
 INIT_TESTS
 
-s_file_begin:
+TRAP_HANDLER m
 
 # Test 5.2.3.6: Test that all the machine mode CSR's are innaccessible for reads and writes in S mode.
 

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-CSR-permission-u-01.S

@@ -25,7 +25,7 @@
 
 INIT_TESTS
 
-s_file_begin:
+TRAP_HANDLER m
 
 # Test 5.2.3.6: Test that all the machine mode CSR's are innaccessible for reads and writes in R mode.
 

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-MMU-SV32.S

@@ -25,7 +25,8 @@
 
 INIT_TESTS
 
-s_file_begin:
+TRAP_HANDLER m
+
 j test_loop_setup // begin test loop/table tests instead of executing inline code.
 
 INIT_TEST_TABLE

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PMA.S

@@ -38,7 +38,8 @@
 
 INIT_TESTS
 
-s_file_begin:
+TRAP_HANDLER m
+
 j test_loop_setup // begin test loop/table tests instead of executing inline code.
 
 INIT_TEST_TABLE

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PMP.S

@@ -25,7 +25,8 @@
 
 INIT_TESTS
 
-s_file_begin:
+TRAP_HANDLER m
+
 j test_loop_setup // begin test loop/table tests instead of executing inline code.
 
 INIT_TEST_TABLE

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h

@@ -52,16 +52,128 @@ RVTEST_CODE_BEGIN
     // address for stack
     la sp, top_of_stack
 
-    // trap handler setup
+.endm
-    la x1, machine_trap_handler
+
-    csrrw x4, mtvec, x1  // x4 reserved for "default" trap handler address that needs to be restored before halting this test.
+// Code to trigger traps goes here so we have consistent mtvals for instruction adresses
+// Even if more tests are added.  
+.macro CAUSE_TRAP_TRIGGERS
+j end_trap_triggers
+
+// The following tests involve causing many of the interrupts and exceptions that are easily done in a few lines
+//      This effectively includes everything that isn't to do with page faults (virtual memory)
+
+cause_instr_addr_misaligned:
+    // cause a misaligned address trap
+    auipc x28, 0      // get current PC, which is aligned
+    addi x28, x28, 0x3  // add 1 to pc to create misaligned address
+    jr x28 // cause instruction address midaligned trap
+    ret
+
+cause_instr_access:
+    la x28, 0x0 // address zero is an address with no memory
+    sw x1, -4(sp) // push the return adress ontot the stack
+    addi sp, sp, -4
+    jalr x28 // cause instruction access trap
+    lw x1, 0(sp) // pop return adress back from the stack
+    addi sp, sp, 4
+    ret
+
+cause_illegal_instr:
+    .word 0x00000000 // a 32 bit zros is an illegal instruction
+    ret
+
+cause_breakpnt: // ****
+    ebreak
+    ret
+
+cause_load_addr_misaligned:
+    auipc x28, 0      // get current PC, which is aligned
+    addi x28, x28, 1
+    lw x29, 0(x28)    // load from a misaligned address
+    ret
+
+cause_load_acc:
+    la x28, 0         // 0 is an address with no memory
+    lw x29, 0(x28)    // load from unimplemented address
+    ret
+
+cause_store_addr_misaligned:
+    auipc x28, 0      // get current PC, which is aligned
+    addi x28, x28, 1
+    sw x29, 0(x28)     // store to a misaligned address
+    ret
+
+cause_store_acc: 
+    la x28, 0         // 0 is an address with no memory
+    sw x29, 0(x28)     // store to unimplemented address
+    ret
+
+cause_ecall:
+    // *** ASSUMES you have already gone to the mode you need to call this from.
+    ecall
+    ret
+
+cause_time_interrupt:
+    // The following code works for both RV32 and RV64.  
+    // RV64 alone would be easier using double-word adds and stores
+    li x28, 0x30          // Desired offset from the present time
+    la x29, 0x02004000    // MTIMECMP register in CLINT
+    la x30, 0x0200BFF8    // MTIME register in CLINT
+    lw x7, 0(x30)         // low word of MTIME
+    lw x31, 4(x30)         // high word of MTIME
+    add x28, x7, x28       // add desired offset to the current time
+    bgtu x28, x7, nowrap  // check new time exceeds current time (no wraparound)
+    addi x31, x31, 1       // if wrap, increment most significant word
+    sw x31,4(x29)          // store into most significant word of MTIMECMP
+nowrap:
+    sw x28, 0(x29)         // store into least significant word of MTIMECMP
+    loop: j loop         // wait until interrupt occurs
+    ret
+
+cause_soft_interrupt:
+    la x28, 0x02000000      // MSIP register in CLINT
+    li x29, 1               // 1 in the lsb
+    sw x29, 0(x28)          // Write MSIP bit
+    ret
+
+cause_ext_interrupt:
+    li x28, 0x10060000 // load base GPIO memory location
+    li x29, 0x1
+    sw x29, 8(x28) // enable the first pin as an output
+    sw x29, 28(x28) // set first pin to high interrupt enable
+    sw x29, 40(x28) // write a 1 to the first output pin (cause interrupt)
+    ret
+
+end_trap_triggers:
+.endm
+
+.macro TRAP_HANDLER MODE, VECTORED=1, DEBUG=0
+    // MODE decides which mode this trap handler will be taken in (M or S mode)
+    // Vectored decides whether interrumpts are handled with the vector table at trap_handler_MODE (1)
+    //      vs Using the non-vector approach the rest of the trap handler takes (0)
+    // DEBUG decides whether we will print mtval a string with status.mpie, status.mie, and status.mpp to the signature (1)
+    //      vs not saving that info to the signature (0)
+
+
+    //   Set up the exception Handler, keeping the original handler in x4.
+    la x1, trap_handler_\MODE\()
+    ori x1, x1, \VECTORED // set mode field of tvec to VECTORED, which will force vectored interrupts if it's 1.
+
+.if (\MODE\() == m)
+    csrrw x4, \MODE\()tvec, x1  // x4 reserved for "default" trap handler address that needs to be restored before halting this test.
+.else
+    csrw \MODE\()tvec, x1 // we only neet save the machine trap handler and this if statement ensures it isn't overwritten
+.endif
+
     li a0, 0
     li a1, 0 
     li a2, 0 // reset trap handler inputs to zero
 
-    // go to beginning of S file where we can decide between using the test data loop
+    la x29, 0x02004000    // MTIMECMP register in CLINT
-    // or using the macro inline code insertion
+    li x30, 0xFFFFFFFF
-    j s_file_begin
+    sw x30, 0(x29) // set mtimecmp to 0xFFFFFFFF to really make sure time interrupts don't go off immediately after being enabled
+
+    j trap_handler_end_\MODE\() // skip the trap handler when it is being defined.
 
 	// ---------------------------------------------------------------------------------------------
     // General traps Handler
@@ -96,38 +208,77 @@ RVTEST_CODE_BEGIN
     // --------------------------------------------------------------------------------------------
 
 
-machine_trap_handler:
+.align 2
+trap_handler_\MODE\():
+    j trap_unvectored_\MODE\() // for the unvectored implimentation: jump past this table of addresses into the actual handler
+    // *** ASSUMES that a cause value of 0 for an interrupt is unimplemented
+    // otherwise, a vectored interrupt handler should jump to trap_handler_\MODE\() + 4 * Interrupt cause code
+    // No matter the value of VECTORED, exceptions (not interrupts) are handled in an unvecotred way
+    j soft_interrupt_\MODE\()    // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table.
+    j segfault_\MODE\()            // 2: reserved
+    j soft_interrupt_\MODE\()    // 3: breakpoint
+    j segfault_\MODE\()            // 4: reserved
+    j time_interrupt_\MODE\()    // 5: load access fault
+    j segfault_\MODE\()            // 6: reserved
+    j time_interrupt_\MODE\()    // 7: store access fault
+    j segfault_\MODE\()            // 8: reserved
+    j ext_interrupt_\MODE\()     // 9: ecall from S-mode
+    j segfault_\MODE\()            // 10: reserved
+    j ext_interrupt_\MODE\()     // 11: ecall from M-mode
+    // 12 through >=16 are reserved or designated for platform use
+
+trap_unvectored_\MODE\():
     // The processor is always in machine mode when a trap takes us here
     // save registers on stack before using
     sw x1, -4(sp)       
     sw x5, -8(sp)      
 
     // Record trap
-    csrr x1, mcause     // record the mcause
+    csrr x1, \MODE\()cause     // record the mcause
     sw x1, 0(x16)        
     addi x6, x6, 4     
     addi x16, x16, 4    // update pointers for logging results
 
+.if (\DEBUG\() == 1) // record extra information (MTVAL, some status bits) about traps
+    csrr x1, \MODE\()tval
+    sw x1, 0(x16)
+    addi x6, x6, 4     
+    addi x16, x16, 4
+
+    csrr x1, \MODE\()status
+    .if (\MODE\() == m) // Taking traps in different modes means we want to get different bits from the status register.
+        li x5, 0x1888 // mask bits to select MPP, MPIE, and MIE.
+    .else
+        li x5, 0x122 // mask bits to select SPP, SPIE, and SIE.
+    .endif
+    and x5, x5, x1
+    sw x5, 0(x16) // store masked out status bits to the output
+    addi x6, x6, 4
+    addi x16, x16, 4
+
+.endif
+
     // Respond to trap based on cause
     // All interrupts should return after being logged
+    csrr x1, \MODE\()cause
     li x5, 0x8000000000000000   // if msb is set, it is an interrupt
     and x5, x5, x1
-    bnez x5, trapreturn   // return from interrupt
+    bnez x5, trapreturn_\MODE\()   // return from interrupt
     // Other trap handling is specified in the vector Table
     slli x1, x1, 2      // multiply cause by 4 to get offset in vector Table
-    la x5, trap_handler_vector_table
+    la x5, exception_vector_table_\MODE\()
     add x5, x5, x1      // compute address of vector in Table
     lw x5, 0(x5)        // fectch address of handler from vector Table
     jr x5               // and jump to the handler
     
-segfault:
+segfault_\MODE\():
     lw x5, -8(sp)      // restore registers from stack before faulting
     lw x1, -4(sp)       
     j terminate_test          // halt program.
 
-trapreturn:
+trapreturn_\MODE\():
     // look at the instruction to figure out whether to add 2 or 4 bytes to PC, or go to address specified in a1
-    csrr x1, mepc       // get the mepc
+    csrr x1, \MODE\()epc       // get the mepc
     addi x1, x1, 4 // *** should be 2 for compressed instructions, see note.
 
 
@@ -151,13 +302,13 @@ trapreturn:
 //     csrr x1, mepc       // get the mepc again    
 //     addi x1, x1, 4      // add 4 to find the next instruction
 
-trapreturn_specified:
+trapreturn_specified_\MODE\():
     // reset the necessary pointers and registers (x1, x5, x6, and the return address going to mepc)
     // so that when we return to a new virtual address, they're all in the right spot as well.
 
-    beqz a1, trapreturn_finished // either update values, of go to default return address.
+    beqz a1, trapreturn_finished_\MODE\() // either update values, of go to default return address.
 
-    la x5, trap_return_pagetype_table
+    la x5, trap_return_pagetype_table_\MODE\()
     slli a2, a2, 2
     add x5, x5, a2
     lw a2, 0(x5) // a2 = number of offset bits in current page type
@@ -189,54 +340,93 @@ trapreturn_specified:
     li a1, 0 
     li a2, 0 // reset trapreturn inputs to the trap handler
 
-trapreturn_finished:
+trapreturn_finished_\MODE\():
-    csrw mepc, x1   // update the mepc with address of next instruction
+    csrw \MODE\()epc, x1   // update the mepc with address of next instruction
     lw x5, -8(sp)   // restore registers from stack before returning
     lw x1, -4(sp)
-    mret  // return from trap
+    \MODE\()ret  // return from trap
 
-ecallhandler:
+ecallhandler_\MODE\():
     // Check input parameter a0. encoding above. 
     // *** ASSUMES: that this trap is being handled in machine mode. in other words, that nothing odd has been written to the medeleg or mideleg csrs.
     li x5, 2            // case 2: change to machine mode
-    beq a0, x5, ecallhandler_changetomachinemode
+    beq a0, x5, ecallhandler_changetomachinemode_\MODE\()
     li x5, 3            // case 3: change to supervisor mode
-    beq a0, x5, ecallhandler_changetosupervisormode
+    beq a0, x5, ecallhandler_changetosupervisormode_\MODE\()
     li x5, 4            // case 4: change to user mode
-    beq a0, x5, ecallhandler_changetousermode
+    beq a0, x5, ecallhandler_changetousermode_\MODE\()
     // unsupported ecalls should segfault
-    j segfault
+    j segfault_\MODE\()
 
-ecallhandler_changetomachinemode:
+ecallhandler_changetomachinemode_\MODE\():
     // Force mstatus.MPP (bits 12:11) to 11 to enter machine mode after mret
     li x1, 0b1100000000000
-    csrs mstatus, x1
+    csrs \MODE\()status, x1
-    j trapreturn        
+    j trapreturn_\MODE\()       
 
-ecallhandler_changetosupervisormode:
+ecallhandler_changetosupervisormode_\MODE\():
     // Force mstatus.MPP (bits 12:11) to 01 to enter supervisor mode after mret
     li x1, 0b1100000000000  
-    csrc mstatus, x1
+    csrc \MODE\()status, x1
     li x1, 0b0100000000000
-    csrs mstatus, x1
+    csrs \MODE\()status, x1
-    j trapreturn
+    j trapreturn_\MODE\()
 
-ecallhandler_changetousermode:
+ecallhandler_changetousermode_\MODE\():
     // Force mstatus.MPP (bits 12:11) to 00 to enter user mode after mret
     li x1, 0b1100000000000  
-    csrc mstatus, x1
+    csrc \MODE\()status, x1
-    j trapreturn
+    j trapreturn_\MODE\()
 
-instrfault:
+instrpagefault_\MODE\():
     lw x1, -4(sp) // load return address int x1 (the address AFTER the jal into faulting page)
-    j trapreturn_finished // puts x1 into mepc, restores stack and returns to program (outside of faulting page)
+    j trapreturn_finished_\MODE\() // puts x1 into mepc, restores stack and returns to program (outside of faulting page)
 
-illegalinstr:
+instrfault_\MODE\():
-    j trapreturn // return to the code after recording the mcause
+    lw x1, -4(sp) // load return address int x1 (the address AFTER the jal to the faulting address)
+    j trapreturn_finished_\MODE\() // return to the code after recording the mcause
 
-accessfault:
+illegalinstr_\MODE\():
+    j trapreturn_\MODE\() // return to the code after recording the mcause
+
+accessfault_\MODE\():
     // *** What do I have to do here?
-    j trapreturn
+    j trapreturn_\MODE\()
+
+addr_misaligned_\MODE\():
+    j trapreturn_\MODE\()
+
+breakpt_\MODE\():
+    j trapreturn_\MODE\()
+
+soft_interrupt_\MODE\():
+    li x5, 0x7EC // write 0x7EC (looks like VEC) to the output before the mcause and extras to indicate that this trap was handled with a vector table. 
+    sw x5, 0(x16)
+    addi x6, x6, 4
+    addi x16, x16, 4
+    la x28, 0x02000000 // Reset by clearing MSIP interrupt from CLINT
+    sw x0, 0(x28)
+    j trap_unvectored_\MODE\()
+
+time_interrupt_\MODE\():
+    li x5, 0x7EC
+    sw x5, 0(x16)
+    addi x6, x6, 4
+    addi x16, x16, 4
+    la x29, 0x02004000    // MTIMECMP register in CLINT
+    li x30, 0xFFFFFFFF
+    sw x30, 0(x29) // reset interrupt by setting mtimecmp to 0xFFFFFFFF
+    j trap_unvectored_\MODE\()
+
+ext_interrupt_\MODE\():
+    li x5, 0x7EC
+    sw x5, 0(x16)
+    addi x6, x6, 4
+    addi x16, x16, 4
+    li x28, 0x10060000 // reset interrupt by clearing all the GPIO bits
+    sw x0, 8(x28) // disable the first pin as an output
+    sw x0, 40(x28) // write a 0 to the first output pin (reset interrupt)
+    j trap_unvectored_\MODE\()
 
     // Table of trap behavior
     // lists what to do on each exception (not interrupts)
@@ -244,29 +434,30 @@ accessfault:
     // Expected exceptions should increment the EPC to the next instruction and return
 
     .align 2 // aligns this data table to an 4 byte boundary
-trap_handler_vector_table:
+exception_vector_table_\MODE\():
-    .4byte segfault      // 0: instruction address misaligned
+    .4byte addr_misaligned_\MODE\()      // 0: instruction address misaligned
-    .4byte instrfault    // 1: instruction access fault
+    .4byte instrfault_\MODE\()    // 1: instruction access fault
-    .4byte illegalinstr  // 2: illegal instruction
+    .4byte illegalinstr_\MODE\()  // 2: illegal instruction
-    .4byte segfault      // 3: breakpoint
+    .4byte breakpt_\MODE\()      // 3: breakpoint
-    .4byte segfault      // 4: load address misaligned
+    .4byte addr_misaligned_\MODE\()      // 4: load address misaligned
-    .4byte accessfault   // 5: load access fault
+    .4byte accessfault_\MODE\()   // 5: load access fault
-    .4byte segfault      // 6: store address misaligned
+    .4byte addr_misaligned_\MODE\()      // 6: store address misaligned
-    .4byte accessfault   // 7: store access fault
+    .4byte accessfault_\MODE\()   // 7: store access fault
-    .4byte ecallhandler  // 8: ecall from U-mode
+    .4byte ecallhandler_\MODE\()  // 8: ecall from U-mode
-    .4byte ecallhandler  // 9: ecall from S-mode
+    .4byte ecallhandler_\MODE\()  // 9: ecall from S-mode
-    .4byte segfault      // 10: reserved
+    .4byte segfault_\MODE\()      // 10: reserved
-    .4byte ecallhandler  // 11: ecall from M-mode
+    .4byte ecallhandler_\MODE\()  // 11: ecall from M-mode
-    .4byte instrfault    // 12: instruction page fault
+    .4byte instrpagefault_\MODE\()    // 12: instruction page fault
-    .4byte trapreturn    // 13: load page fault
+    .4byte trapreturn_\MODE\()    // 13: load page fault
-    .4byte segfault      // 14: reserved
+    .4byte segfault_\MODE\()      // 14: reserved
-    .4byte trapreturn    // 15: store page fault
+    .4byte trapreturn_\MODE\()    // 15: store page fault
 
 .align 2
-trap_return_pagetype_table:
+trap_return_pagetype_table_\MODE\():
     .4byte 0xC  // 0: kilopage has 12 offset bits
     .4byte 0x16 // 1: megapage has 22 offset bits
 
+trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler and continue with the test
 .endm
 
 // Test Summary table!
@@ -367,7 +558,7 @@ trap_return_pagetype_table:
 // they generally do not fault or cause issues as long as these modes are enabled 
 // *** add functionality to check if modes are enabled before jumping? maybe cause a fault if not?
 
-.macro GOTO_M_MODE RETURN_VPN RETURN_PAGETYPE
+.macro GOTO_M_MODE RETURN_VPN=0x0 RETURN_PAGETYPE=0x0
     li a0, 2 // determine trap handler behavior (go to machine mode)
     li a1, \RETURN_VPN // return VPN
     li a2, \RETURN_PAGETYPE // return page types
@@ -375,7 +566,7 @@ trap_return_pagetype_table:
     // now in S mode
 .endm
 
-.macro GOTO_S_MODE RETURN_VPN RETURN_PAGETYPE
+.macro GOTO_S_MODE RETURN_VPN=0x0 RETURN_PAGETYPE=0x0
     li a0, 3 // determine trap handler behavior (go to supervisor mode)
     li a1, \RETURN_VPN // return VPN
     li a2, \RETURN_PAGETYPE // return page types
@@ -383,7 +574,7 @@ trap_return_pagetype_table:
     // now in S mode
 .endm
 
-.macro GOTO_U_MODE RETURN_VPN RETURN_PAGETYPE
+.macro GOTO_U_MODE RETURN_VPN=0x0 RETURN_PAGETYPE=0x0
     li a0, 4 // determine trap handler behavior (go to user mode)
     li a1, \RETURN_VPN // return VPN
     li a2, \RETURN_PAGETYPE // return page types

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-minfo-01.S

@@ -25,7 +25,7 @@
 
 INIT_TESTS
 
-s_file_begin:
+TRAP_HANDLER m
 
 // Test 5.2.3.1: testing Read-only access to Machine info CSRs 
 CSR_R_ACCESS mvendorid

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-misa-01.S

@@ -25,7 +25,7 @@
 
 INIT_TESTS
 
-s_file_begin:
+TRAP_HANDLER m
 // Test 5.3.2.2: Machine ISA register test
 
 // Misa is a specific case *** so I don't want to add a whole test case for reading nonzero but unkown value CSRs.

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mtvec-01.S

@@ -0,0 +1,45 @@
+///////////////////////////////////////////
+//
+// WALLY-unvectored-interrupt
+//
+// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
+//
+// Created 2022-03-11
+//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+#include "WALLY-TEST-LIB-64.h"
+
+INIT_TESTS
+
+// test 5.3.1.5 Unvectored interrupt tests 
+
+TRAP_HANDLER m, VECTORED=0, DEBUG=1 // turn off vectored interrupts, while turning on recording of mstatus bits.
+
+li x28, 0x8
+csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode
+WRITE_READ_CSR mie, 0xFFF // *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts
+
+// cause traps, ensuring that we DONT go through the vectored part of the trap handler
+// *** this assumes that interrupt code 0 remains reserved
+
+CAUSE_TIME_INTERRUPT // *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. 
+CAUSE_SOFT_INTERRUPT // *** exiting out of the trap handler after these is current;y broken
+CAUSE_EXT_INTERRUPT
+
+END_TESTS
+
+TEST_STACK_AND_DATA

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-scratch-01.S

@@ -25,7 +25,8 @@
 
 INIT_TESTS
 
-s_file_begin:
+TRAP_HANDLER m
+
 // Test 5.3.2.3: Scratch registers test
 
 WRITE_READ_CSR mscratch, 0x111 // check that mscratch is readable and writeable in machine mode

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-sscratch-s-01.S

@@ -25,7 +25,7 @@
 
 INIT_TESTS
 
-s_file_begin:
+TRAP_HANDLER m
 
 // Test 5.3.2.3: Scratch registers test
 WRITE_READ_CSR sscratch, 0x111 // check that sscratch is readable and writeable in machine mode

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-stvec-01.S

@@ -0,0 +1,55 @@
+///////////////////////////////////////////
+//
+// WALLY-unvectored-interrupt
+//
+// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
+//
+// Created 2022-03-11
+//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+#include "WALLY-TEST-LIB-64.h"
+
+INIT_TESTS
+
+// test 5.3.1.5 Unvectored interrupt tests 
+
+TRAP_HANDLER s, VECTORED=0, DEBUG=1 // turn off vectored interrupts, while turning on recording of mstatus bits.
+
+// li x28, 0x8
+// csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode
+// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts
+
+WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
+
+GOTO_S_MODE
+
+// cause traps, ensuring that we DONT go through the vectored part of the trap handler
+// *** this assumes that interrupt code 0 remains reserved
+
+// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. 
+// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
+// CAUSE_EXT_INTERRUPT
+
+GOTO_U_MODE 
+
+// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. 
+// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
+// CAUSE_EXT_INTERRUPT
+
+END_TESTS
+
+TEST_STACK_AND_DATA

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-01.S

@@ -0,0 +1,76 @@
+///////////////////////////////////////////
+//
+// WALLY-trap
+//
+// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
+//
+// Created 2022-02-20
+//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+#include "WALLY-TEST-LIB-64.h"
+
+INIT_TESTS
+
+CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
+
+TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps
+
+li x28, 0x8
+csrs mstatus, x28 // set mstatus.MIE bit to 1
+WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources // *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts
+
+// test 5.3.1.4 Basic trap tests 
+
+// jal cause_instr_addr_misaligned //skipped becuase this exception may be impossible when compressed instructions are enabled)
+jal cause_instr_access
+jal cause_illegal_instr
+jal cause_breakpnt
+jal cause_load_addr_misaligned
+jal cause_load_acc
+jal cause_store_addr_misaligned
+jal cause_store_acc
+GOTO_U_MODE // Causes M mode ecall
+GOTO_S_MODE // Causes U mode ecall
+GOTO_M_MODE // Causes S mode ecall
+
+jal cause_time_interrupt // *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. 
+jal cause_soft_interrupt // *** exiting out of the trap handler after these is current;y broken
+jal cause_ext_interrupt
+
+// try the traps again with mideleg = medeleg = all 1's to ensure traps still go to M mode from M mode
+
+WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF
+WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
+
+// jal cause_instr_addr_misaligned //skipped becuase this exception may be impossible when compressed instructions are enabled)
+jal cause_instr_access
+jal cause_illegal_instr
+jal cause_breakpnt
+jal cause_load_addr_misaligned
+jal cause_load_acc
+jal cause_store_addr_misaligned
+jal cause_store_acc
+jal cause_ecall // M mode ecall
+
+jal cause_time_interrupt // *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. 
+jal cause_soft_interrupt // *** exiting out of the trap handler after these is current;y broken
+jal cause_ext_interrupt
+
+END_TESTS
+
+TEST_STACK_AND_DATA
+

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S

@@ -0,0 +1,85 @@
+///////////////////////////////////////////
+//
+// WALLY-trap-s
+//
+// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
+//
+// Created 2022-03-11
+//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+#include "WALLY-TEST-LIB-64.h"
+
+INIT_TESTS
+
+// test 5.3.1.4 Basic trap tests 
+
+TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps
+TRAP_HANDLER s, DEBUG=1 // have S mode trap handler as well
+
+// Like WALLY-trap, cause all the same traps from S mode and make sure they go to machine mode with zeroed mideleg, medeleg
+
+GOTO_S_MODE
+
+li x28, 0x8
+csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode
+// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts
+
+
+// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled)
+CAUSE_INSTR_ACCESS
+CAUSE_ILLEGAL_INSTR
+CAUSE_BREAKPNT
+CAUSE_LOAD_ADDR_MISALIGNED
+CAUSE_LOAD_ACC
+CAUSE_STORE_ADDR_MISALIGNED
+CAUSE_STORE_ACC
+CAUSE_ECALL
+
+// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. 
+// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
+// CAUSE_EXT_INTERRUPT
+
+
+// Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler
+// We can tell which one becuase the different trap handler modes write different bits of the status register 
+// to the output when debug is on.
+
+GOTO_M_MODE // so we can write the delegate registers
+
+WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF
+WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
+
+GOTO_S_MODE
+
+// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled)
+CAUSE_INSTR_ACCESS
+CAUSE_ILLEGAL_INSTR
+CAUSE_BREAKPNT
+CAUSE_LOAD_ADDR_MISALIGNED
+CAUSE_LOAD_ACC
+CAUSE_STORE_ADDR_MISALIGNED
+CAUSE_STORE_ACC
+CAUSE_ECALL
+
+// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. 
+// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
+// CAUSE_EXT_INTERRUPT
+
+END_TESTS
+
+TEST_STACK_AND_DATA
+

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S

@@ -0,0 +1,84 @@
+///////////////////////////////////////////
+//
+// WALLY-trap-u
+//
+// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
+//
+// Created 2022-03-11
+//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+#include "WALLY-TEST-LIB-64.h"
+
+INIT_TESTS
+
+// test 5.3.1.4 Basic trap tests 
+
+TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps
+TRAP_HANDLER s, DEBUG=1 // have S mode trap handler as well
+
+// Like WALLY-trap, cause all the same traps from U mode and make sure they go to machine mode with zeroed mideleg, medeleg
+
+GOTO_U_MODE
+
+// li x28, 0x8
+// csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode
+// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts
+
+
+// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled)
+CAUSE_INSTR_ACCESS
+CAUSE_ILLEGAL_INSTR
+CAUSE_BREAKPNT
+CAUSE_LOAD_ADDR_MISALIGNED
+CAUSE_LOAD_ACC
+CAUSE_STORE_ADDR_MISALIGNED
+CAUSE_STORE_ACC
+CAUSE_ECALL
+
+// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. 
+// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
+// CAUSE_EXT_INTERRUPT
+
+
+// Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler
+// We can tell which one becuase the different trap handler modes write different bits of the status register 
+// to the output when debug is on.
+
+GOTO_M_MODE // so we can write the delegate registers
+
+WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF
+WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
+
+GOTO_U_MODE
+
+// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled)
+CAUSE_INSTR_ACCESS
+CAUSE_ILLEGAL_INSTR
+CAUSE_BREAKPNT
+CAUSE_LOAD_ADDR_MISALIGNED
+CAUSE_LOAD_ACC
+CAUSE_STORE_ADDR_MISALIGNED
+CAUSE_STORE_ACC
+CAUSE_ECALL
+
+// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. 
+// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
+// CAUSE_EXT_INTERRUPT
+
+END_TESTS
+
+TEST_STACK_AND_DATA

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h

@@ -117,7 +117,7 @@ cause_ecall:
 cause_time_interrupt:
     // The following code works for both RV32 and RV64.  
     // RV64 alone would be easier using double-word adds and stores
-    li x28, 0x100          // Desired offset from the present time
+    li x28, 0x30          // Desired offset from the present time
     la x29, 0x02004000    // MTIMECMP register in CLINT
     la x30, 0x0200BFF8    // MTIME register in CLINT
     lw x7, 0(x30)         // low word of MTIME
@@ -158,9 +158,7 @@ end_trap_triggers:
 
     //   Set up the exception Handler, keeping the original handler in x4.
     la x1, trap_handler_\MODE\()
-.if (\VECTORED\() == 1)
+    ori x1, x1, \VECTORED // set mode field of tvec to VECTORED, which will force vectored interrupts if it's 1.
-    ori x1, x1, 0x1 // set mode field of tvec to 1, forcing vectored interrupts
-.endif
 
 .if (\MODE\() == m)
     csrrw x4, \MODE\()tvec, x1  // x4 reserved for "default" trap handler address that needs to be restored before halting this test.
@@ -172,6 +170,10 @@ end_trap_triggers:
     li a1, 0 
     li a2, 0 // reset trap handler inputs to zero
 
+    la x29, 0x02004000    // MTIMECMP register in CLINT
+    li x30, 0xFFFFFFFF
+    sd x30, 0(x29) // set mtimecmp to 0xFFFFFFFF to really make sure time interrupts don't go off immediately after being enabled
+
     j trap_handler_end_\MODE\() // skip the trap handler when it is being defined.
 
 	// ---------------------------------------------------------------------------------------------
@@ -214,17 +216,17 @@ trap_handler_\MODE\():
     // *** ASSUMES that a cause value of 0 for an interrupt is unimplemented
     // otherwise, a vectored interrupt handler should jump to trap_handler_\MODE\() + 4 * Interrupt cause code
     // No matter the value of VECTORED, exceptions (not interrupts) are handled in an unvecotred way
-    j s_soft_interrupt_\MODE\()    // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table.
+    j soft_interrupt_\MODE\()    // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table.
     j segfault_\MODE\()            // 2: reserved
-    j m_soft_interrupt_\MODE\()    // 3: breakpoint
+    j soft_interrupt_\MODE\()    // 3: breakpoint
     j segfault_\MODE\()            // 4: reserved
-    j s_time_interrupt_\MODE\()    // 5: load access fault
+    j time_interrupt_\MODE\()    // 5: load access fault
     j segfault_\MODE\()            // 6: reserved
-    j m_time_interrupt_\MODE\()    // 7: store access fault
+    j time_interrupt_\MODE\()    // 7: store access fault
     j segfault_\MODE\()            // 8: reserved
-    j s_ext_interrupt_\MODE\()     // 9: ecall from S-mode
+    j ext_interrupt_\MODE\()     // 9: ecall from S-mode
     j segfault_\MODE\()            // 10: reserved
-    j m_ext_interrupt_\MODE\()     // 11: ecall from M-mode
+    j ext_interrupt_\MODE\()     // 11: ecall from M-mode
     // 12 through >=16 are reserved or designated for platform use
 
 trap_unvectored_\MODE\():
@@ -245,12 +247,11 @@ trap_unvectored_\MODE\():
     addi x16, x16, 8
 
     csrr x1, \MODE\()status
-.if (\MODE\() == m) // Taking traps in different modes means we want to get different bits from the status register.
+    .if (\MODE\() == m) // Taking traps in different modes means we want to get different bits from the status register.
-    li x5, 0x1888 // mask bits to select MPP, MPIE, and MIE.
+        li x5, 0x1888 // mask bits to select MPP, MPIE, and MIE.
-.else
+    .else
-    li x5, 0x122 // mask bits to select SPP, SPIE, and SIE.
+        li x5, 0x122 // mask bits to select SPP, SPIE, and SIE.
-.endif
+    .endif
-
     and x5, x5, x1
     sd x5, 0(x16) // store masked out status bits to the output
     addi x6, x6, 8
@@ -265,7 +266,6 @@ trap_unvectored_\MODE\():
     and x5, x5, x1
     bnez x5, trapreturn_\MODE\()   // return from interrupt
     // Other trap handling is specified in the vector Table
-    csrr x1, \MODE\()cause
     slli x1, x1, 3      // multiply cause by 8 to get offset in vector Table
     la x5, exception_vector_table_\MODE\()
     add x5, x5, x1      // compute address of vector in Table
@@ -345,7 +345,7 @@ trapreturn_finished_\MODE\():
     csrw \MODE\()epc, x1       // update the epc with address of next instruction
     ld x5, -16(sp)      // restore registers from stack before returning
     ld x1, -8(sp)
-    csrw \MODE\()ip, 0x0 // clear interrupt pending register to indicate interrupt has been handled
+    // *** this should be handled by indirectly clearing this bit csrw \MODE\()ip, 0x0 // clear interrupt pending register to indicate interrupt has been handled
     \MODE\()ret  // return from trap
 
 ecallhandler_\MODE\():
@@ -376,7 +376,7 @@ ecallhandler_changetosupervisormode_\MODE\():
 ecallhandler_changetousermode_\MODE\():
     // Force mstatus.MPP (bits 12:11) to 00 to enter user mode after mret
     li x1, 0b1100000000000  
-    csrc mstatus, x1
+    csrc \MODE\()status, x1
     j trapreturn_\MODE\()
 
 instrpagefault_\MODE\():
@@ -400,7 +400,7 @@ addr_misaligned_\MODE\():
 breakpt_\MODE\():
     j trapreturn_\MODE\()
 
-s_soft_interrupt_\MODE\(): // these labels are here to make sure the code compiles, but don't actually do anything yet
+soft_interrupt_\MODE\():
     li x5, 0x7EC // write 0x7EC (looks like VEC) to the output before the mcause and extras to indicate that this trap was handled with a vector table. 
     sd x5, 0(x16)
     addi x6, x6, 8
@@ -409,30 +409,19 @@ s_soft_interrupt_\MODE\(): // these labels are here to make sure the code compil
     sw x0, 0(x28)
     j trap_unvectored_\MODE\()
 
-m_soft_interrupt_\MODE\():
+time_interrupt_\MODE\():
     li x5, 0x7EC
     sd x5, 0(x16)
     addi x6, x6, 8
     addi x16, x16, 8
-    la x28, 0x02000000 // Reset by clearing MSIP interrupt from CLINT
+
-    sw x0, 0(x28)
+    la x29, 0x02004000    // MTIMECMP register in CLINT
+    li x30, 0xFFFFFFFF
+    sd x30, 0(x29) // reset interrupt by setting mtimecmp to 0xFFFFFFFF
+
     j trap_unvectored_\MODE\()
 
-s_time_interrupt_\MODE\():
+ext_interrupt_\MODE\():
-    li x5, 0x7EC
-    sd x5, 0(x16)
-    addi x6, x6, 8
-    addi x16, x16, 8
-    j trap_unvectored_\MODE\()
-
-m_time_interrupt_\MODE\():
-    li x5, 0x7EC
-    sd x5, 0(x16)
-    addi x6, x6, 8
-    addi x16, x16, 8
-    j trap_unvectored_\MODE\()
-
-s_ext_interrupt_\MODE\():
     li x5, 0x7EC
     sd x5, 0(x16)
     addi x6, x6, 8
@@ -442,17 +431,6 @@ s_ext_interrupt_\MODE\():
     sw x0, 40(x28) // write a 0 to the first output pin (reset interrupt)
     j trap_unvectored_\MODE\()
 
-m_ext_interrupt_\MODE\():
-    li x5, 0x7EC
-    sd x5, 0(x16)
-    addi x6, x6, 8
-    addi x16, x16, 8
-    li x28, 0x10060000 // reset interrupt by clearing all the GPIO bits
-    sw x0, 8(x28) // disable the first pin as an output
-    sw x0, 40(x28) // write a 0 to the first output pin (reset interrupt)
-    j trap_unvectored_\MODE\()
-
-
     // Table of trap behavior
     // lists what to do on each exception (not interrupts)
     // unexpected exceptions should cause segfaults for easy detection
@@ -720,87 +698,6 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a
     addi x16, x16, 8 
 .endm
 
-// // The following tests involve causing many of the interrupts and exceptions that are easily done in a few lines
-// //      This effectively includes everything that isn't to do with page faults (virtual memory)
-
-// .macro CAUSE_INSTR_ADDR_MISALIGNED
-//     // cause a misaligned address trap
-//     auipc x28, 0      // get current PC, which is aligned
-//     addi x28, x28, 0x1  // add 1 to pc to create misaligned address
-//     jalr x28 // cause instruction address midaligned trap
-// .endm
-
-// .macro CAUSE_INSTR_ACCESS
-//     la x28, 0x0 // address zero is an address with no memory
-//     jalr x28 // cause instruction access trap
-// .endm
-
-// .macro CAUSE_ILLEGAL_INSTR
-//     .word 0x00000000 // a 32 bit zros is an illegal instruction
-// .endm
-
-// .macro CAUSE_BREAKPNT // ****
-//     ebreak
-// .endm
-
-// .macro CAUSE_LOAD_ADDR_MISALIGNED
-//     auipc x28, 0      // get current PC, which is aligned
-//     addi x28, x28, 1
-//     lw x29, 0(x28)    // load from a misaligned address
-// .endm
-
-// .macro CAUSE_LOAD_ACC
-//     la x28, 0         // 0 is an address with no memory
-//     lw x29, 0(x28)    // load from unimplemented address
-// .endm
-
-// .macro CAUSE_STORE_ADDR_MISALIGNED
-//     auipc x28, 0      // get current PC, which is aligned
-//     addi x28, x28, 1
-//     sw x29, 0(x28)     // store to a misaligned address
-// .endm
-
-// .macro CAUSE_STORE_ACC 
-//     la x28, 0         // 0 is an address with no memory
-//     sw x29, 0(x28)     // store to unimplemented address
-// .endm
-
-// .macro CAUSE_ECALL
-//     // *** ASSUMES you have already gone to the mode you need to call this from.
-//     ecall
-// .endm
-
-// .macro CAUSE_TIME_INTERRUPT
-//     // The following code works for both RV32 and RV64.  
-//     // RV64 alone would be easier using double-word adds and stores
-//     li x28, 0x100          // Desired offset from the present time
-//     la x29, 0x02004000    // MTIMECMP register in CLINT
-//     la x30, 0x0200BFF8    // MTIME register in CLINT
-//     lw x7, 0(x30)         // low word of MTIME
-//     lw x31, 4(x30)         // high word of MTIME
-//     add x28, x7, x28       // add desired offset to the current time
-//     bgtu x28, x7, nowrap  // check new time exceeds current time (no wraparound)
-//     addi x31, x31, 1       // if wrap, increment most significant word
-//     sw x31,4(x29)          // store into most significant word of MTIMECMP
-// nowrap:
-//     sw x28, 0(x29)         // store into least significant word of MTIMECMP
-//     loop: j loop         // wait until interrupt occurs
-// .endm
-
-// .macro CAUSE_SOFT_INTERRUPT
-//     la x28, 0x02000000      // MSIP register in CLINT
-//     li x29, 1               // 1 in the lsb
-//     sw x29, 0(x28)          // Write MSIP bit
-// .endm
-
-// .macro CAUSE_EXT_INTERRUPT
-//     li x28, 0x10060000 // load base GPIO memory location
-//     li x29, 0x1
-//     sw x29, 8(x28) // enable the first pin as an output
-//     sw x29, 28(x28) // set first pin to high interrupt enable
-//     sw x29, 40(x28) // write a 1 to the first output pin (cause interrupt)
-// .endm
-
 .macro END_TESTS
     // invokes one final ecall to return to machine mode then terminates this program, so the output is
     //      0x8: termination called from U mode