diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc
index 8eb3e2b3..6ec637c6 100644
--- a/fpga/constraints/debug2.xdc
+++ b/fpga/constraints/debug2.xdc
@@ -562,9 +562,9 @@ connect_debug_port u_ila_0/probe120 [get_nets [list {wallypipelinedsoc/core/lsu/
 
 
 create_debug_port u_ila_0 probe
-set_property port_width 56 [get_debug_ports u_ila_0/probe121]
+set_property port_width 64 [get_debug_ports u_ila_0/probe121]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe121]
-connect_debug_port u_ila_0/probe121 [get_nets [list {wallypipelinedsoc/core/lsu/IEUAdrM[0]} {wallypipelinedsoc/core/lsu/IEUAdrM[1]} {wallypipelinedsoc/core/lsu/IEUAdrM[2]} {wallypipelinedsoc/core/lsu/IEUAdrM[3]} {wallypipelinedsoc/core/lsu/IEUAdrM[4]} {wallypipelinedsoc/core/lsu/IEUAdrM[5]} {wallypipelinedsoc/core/lsu/IEUAdrM[6]} {wallypipelinedsoc/core/lsu/IEUAdrM[7]} {wallypipelinedsoc/core/lsu/IEUAdrM[8]} {wallypipelinedsoc/core/lsu/IEUAdrM[9]} {wallypipelinedsoc/core/lsu/IEUAdrM[10]} {wallypipelinedsoc/core/lsu/IEUAdrM[11]} {wallypipelinedsoc/core/lsu/IEUAdrM[12]} {wallypipelinedsoc/core/lsu/IEUAdrM[13]} {wallypipelinedsoc/core/lsu/IEUAdrM[14]} {wallypipelinedsoc/core/lsu/IEUAdrM[15]} {wallypipelinedsoc/core/lsu/IEUAdrM[16]} {wallypipelinedsoc/core/lsu/IEUAdrM[17]} {wallypipelinedsoc/core/lsu/IEUAdrM[18]} {wallypipelinedsoc/core/lsu/IEUAdrM[19]} {wallypipelinedsoc/core/lsu/IEUAdrM[20]} {wallypipelinedsoc/core/lsu/IEUAdrM[21]} {wallypipelinedsoc/core/lsu/IEUAdrM[22]} {wallypipelinedsoc/core/lsu/IEUAdrM[23]} {wallypipelinedsoc/core/lsu/IEUAdrM[24]} {wallypipelinedsoc/core/lsu/IEUAdrM[25]} {wallypipelinedsoc/core/lsu/IEUAdrM[26]} {wallypipelinedsoc/core/lsu/IEUAdrM[27]} {wallypipelinedsoc/core/lsu/IEUAdrM[28]} {wallypipelinedsoc/core/lsu/IEUAdrM[29]} {wallypipelinedsoc/core/lsu/IEUAdrM[30]} {wallypipelinedsoc/core/lsu/IEUAdrM[31]} {wallypipelinedsoc/core/lsu/IEUAdrM[32]} {wallypipelinedsoc/core/lsu/IEUAdrM[33]} {wallypipelinedsoc/core/lsu/IEUAdrM[34]} {wallypipelinedsoc/core/lsu/IEUAdrM[35]} {wallypipelinedsoc/core/lsu/IEUAdrM[36]} {wallypipelinedsoc/core/lsu/IEUAdrM[37]} {wallypipelinedsoc/core/lsu/IEUAdrM[38]} {wallypipelinedsoc/core/lsu/IEUAdrM[39]} {wallypipelinedsoc/core/lsu/IEUAdrM[40]} {wallypipelinedsoc/core/lsu/IEUAdrM[41]} {wallypipelinedsoc/core/lsu/IEUAdrM[42]} {wallypipelinedsoc/core/lsu/IEUAdrM[43]} {wallypipelinedsoc/core/lsu/IEUAdrM[44]} {wallypipelinedsoc/core/lsu/IEUAdrM[45]} {wallypipelinedsoc/core/lsu/IEUAdrM[46]} {wallypipelinedsoc/core/lsu/IEUAdrM[47]} {wallypipelinedsoc/core/lsu/IEUAdrM[48]} {wallypipelinedsoc/core/lsu/IEUAdrM[49]} {wallypipelinedsoc/core/lsu/IEUAdrM[50]} {wallypipelinedsoc/core/lsu/IEUAdrM[51]} {wallypipelinedsoc/core/lsu/IEUAdrM[52]} {wallypipelinedsoc/core/lsu/IEUAdrM[53]} {wallypipelinedsoc/core/lsu/IEUAdrM[54]} {wallypipelinedsoc/core/lsu/IEUAdrM[55]} ]]
+connect_debug_port u_ila_0/probe121 [get_nets [list {wallypipelinedsoc/core/SrcAM[0]} {wallypipelinedsoc/core/SrcAM[1]} {wallypipelinedsoc/core/SrcAM[2]} {wallypipelinedsoc/core/SrcAM[3]} {wallypipelinedsoc/core/SrcAM[4]} {wallypipelinedsoc/core/SrcAM[5]} {wallypipelinedsoc/core/SrcAM[6]} {wallypipelinedsoc/core/SrcAM[7]} {wallypipelinedsoc/core/SrcAM[8]} {wallypipelinedsoc/core/SrcAM[9]} {wallypipelinedsoc/core/SrcAM[10]} {wallypipelinedsoc/core/SrcAM[11]} {wallypipelinedsoc/core/SrcAM[12]} {wallypipelinedsoc/core/SrcAM[13]} {wallypipelinedsoc/core/SrcAM[14]} {wallypipelinedsoc/core/SrcAM[15]} {wallypipelinedsoc/core/SrcAM[16]} {wallypipelinedsoc/core/SrcAM[17]} {wallypipelinedsoc/core/SrcAM[18]} {wallypipelinedsoc/core/SrcAM[19]} {wallypipelinedsoc/core/SrcAM[20]} {wallypipelinedsoc/core/SrcAM[21]} {wallypipelinedsoc/core/SrcAM[22]} {wallypipelinedsoc/core/SrcAM[23]} {wallypipelinedsoc/core/SrcAM[24]} {wallypipelinedsoc/core/SrcAM[25]} {wallypipelinedsoc/core/SrcAM[26]} {wallypipelinedsoc/core/SrcAM[27]} {wallypipelinedsoc/core/SrcAM[28]} {wallypipelinedsoc/core/SrcAM[29]} {wallypipelinedsoc/core/SrcAM[30]} {wallypipelinedsoc/core/SrcAM[31]} {wallypipelinedsoc/core/SrcAM[32]} {wallypipelinedsoc/core/SrcAM[33]} {wallypipelinedsoc/core/SrcAM[34]} {wallypipelinedsoc/core/SrcAM[35]} {wallypipelinedsoc/core/SrcAM[36]} {wallypipelinedsoc/core/SrcAM[37]} {wallypipelinedsoc/core/SrcAM[38]} {wallypipelinedsoc/core/SrcAM[39]} {wallypipelinedsoc/core/SrcAM[40]} {wallypipelinedsoc/core/SrcAM[41]} {wallypipelinedsoc/core/SrcAM[42]} {wallypipelinedsoc/core/SrcAM[43]} {wallypipelinedsoc/core/SrcAM[44]} {wallypipelinedsoc/core/SrcAM[45]} {wallypipelinedsoc/core/SrcAM[46]} {wallypipelinedsoc/core/SrcAM[47]} {wallypipelinedsoc/core/SrcAM[48]} {wallypipelinedsoc/core/SrcAM[49]} {wallypipelinedsoc/core/SrcAM[50]} {wallypipelinedsoc/core/SrcAM[51]} {wallypipelinedsoc/core/SrcAM[52]} {wallypipelinedsoc/core/SrcAM[53]} {wallypipelinedsoc/core/SrcAM[54]} {wallypipelinedsoc/core/SrcAM[55]} {wallypipelinedsoc/core/SrcAM[56]} {wallypipelinedsoc/core/SrcAM[57]} {wallypipelinedsoc/core/SrcAM[58]} {wallypipelinedsoc/core/SrcAM[59]} {wallypipelinedsoc/core/SrcAM[60]} {wallypipelinedsoc/core/SrcAM[61]} {wallypipelinedsoc/core/SrcAM[62]} {wallypipelinedsoc/core/SrcAM[63]}]]
 
 
 create_debug_port u_ila_0 probe
@@ -599,18 +599,18 @@ connect_debug_port u_ila_0/probe126 [get_nets [list {wallypipelinedsoc/core/lsu/
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe127]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe127]
-connect_debug_port u_ila_0/probe127 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[63]} ]]
+connect_debug_port u_ila_0/probe127 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[0]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[1]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[2]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[3]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[4]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[5]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[6]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[7]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[8]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[9]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[10]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[11]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[12]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[13]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[14]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[15]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[16]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[17]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[18]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[19]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[20]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[21]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[22]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[23]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[24]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[25]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[26]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[27]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[28]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[29]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[30]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[31]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[32]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[33]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[34]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[35]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[36]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[37]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[38]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[39]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[40]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[41]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[42]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[43]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[44]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[45]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[46]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[47]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[48]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[49]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[50]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[51]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[52]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[53]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[54]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[55]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[56]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[57]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[58]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[59]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[60]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[61]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[62]} {wallypipelinedsoc/core/priv.priv/csr/CSRReadValM[63]} ]]
 
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe128]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe128]
-connect_debug_port u_ila_0/probe128 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MSCRATCH_REGW[63]} ]]
+connect_debug_port u_ila_0/probe128 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[0]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[1]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[2]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[3]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[4]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[5]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[6]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[7]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[8]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[9]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[10]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[11]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[12]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[13]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[14]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[15]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[16]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[17]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[18]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[19]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[20]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[21]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[22]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[23]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[24]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[25]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[26]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[27]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[28]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[29]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[30]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[31]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[32]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[33]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[34]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[35]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[36]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[37]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[38]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[39]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[40]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[41]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[42]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[43]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[44]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[45]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[46]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[47]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[48]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[49]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[50]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[51]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[52]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[53]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[54]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[55]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[56]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[57]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[58]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[59]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[60]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[61]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[62]} {wallypipelinedsoc/core/priv.priv/csr/CSRSrcM[63]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe129]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe129]
-connect_debug_port u_ila_0/probe129 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[4]__0[63]} ]]
+connect_debug_port u_ila_0/probe129 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[0]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[1]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[2]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[3]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[4]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[5]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[6]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[7]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[8]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[9]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[10]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[11]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[12]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[13]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[14]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[15]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[16]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[17]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[18]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[19]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[20]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[21]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[22]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[23]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[24]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[25]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[26]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[27]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[28]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[29]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[30]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[31]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[32]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[33]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[34]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[35]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[36]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[37]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[38]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[39]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[40]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[41]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[42]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[43]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[44]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[45]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[46]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[47]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[48]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[49]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[50]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[51]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[52]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[53]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[54]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[55]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[56]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[57]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[58]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[59]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[60]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[61]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[62]} {wallypipelinedsoc/core/priv.priv/csr/CSRWriteValM[63]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe130]
@@ -651,3 +651,70 @@ create_debug_port u_ila_0 probe
 set_property port_width 12 [get_debug_ports u_ila_0/probe137]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe137]
 connect_debug_port u_ila_0/probe137 [get_nets [list {wallypipelinedsoc/uncore/plic.plic/intPending[1]} {wallypipelinedsoc/uncore/plic.plic/intPending[2]} {wallypipelinedsoc/uncore/plic.plic/intPending[3]} {wallypipelinedsoc/uncore/plic.plic/intPending[4]} {wallypipelinedsoc/uncore/plic.plic/intPending[5]} {wallypipelinedsoc/uncore/plic.plic/intPending[6]} {wallypipelinedsoc/uncore/plic.plic/intPending[7]} {wallypipelinedsoc/uncore/plic.plic/intPending[8]} {wallypipelinedsoc/uncore/plic.plic/intPending[9]} {wallypipelinedsoc/uncore/plic.plic/intPending[10]} {wallypipelinedsoc/uncore/plic.plic/intPending[11]} {wallypipelinedsoc/uncore/plic.plic/intPending[12]}]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 12 [get_debug_ports u_ila_0/probe138]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe138]
+connect_debug_port u_ila_0/probe138 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[0]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[1]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[2]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[3]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[4]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[5]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[6]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[7]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[8]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[9]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[10]} {wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[11]}]]
+
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe139]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe139]
+connect_debug_port u_ila_0/probe139 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/MExtIntM}]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe140]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe140]
+connect_debug_port u_ila_0/probe140 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/SExtIntM} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe141]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe141]
+connect_debug_port u_ila_0/probe141 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/TimerIntM} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe142]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe142]
+connect_debug_port u_ila_0/probe142 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csri/SwIntM} ]]
+
+
+create_debug_port u_ila_0 probe
+set_property port_width 70 [get_debug_ports u_ila_0/probe143]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe143]
+connect_debug_port u_ila_0/probe143 [get_nets [list {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][10]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][1]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][2]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][3]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][4]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][5]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][6]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][7]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][8]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][9]} {wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][10]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 3 [get_debug_ports u_ila_0/probe144]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe144]
+connect_debug_port u_ila_0/probe144 [get_nets [list {wallypipelinedsoc/uncore/plic.plic/intPriority[10][0]} {wallypipelinedsoc/uncore/plic.plic/intPriority[10][1]} {wallypipelinedsoc/uncore/plic.plic/intPriority[10][2]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 10 [get_debug_ports u_ila_0/probe145]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe145]
+connect_debug_port u_ila_0/probe145 [get_nets [list {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[1]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[2]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[3]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[4]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[5]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[6]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[7]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[8]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[9]} {wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[10]} ]]
+
+
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe146]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe146]
+connect_debug_port u_ila_0/probe146 [get_nets [list {wallypipelinedsoc/uncore/clint.clint/MTIME[0]} {wallypipelinedsoc/uncore/clint.clint/MTIME[1]} {wallypipelinedsoc/uncore/clint.clint/MTIME[2]} {wallypipelinedsoc/uncore/clint.clint/MTIME[3]} {wallypipelinedsoc/uncore/clint.clint/MTIME[4]} {wallypipelinedsoc/uncore/clint.clint/MTIME[5]} {wallypipelinedsoc/uncore/clint.clint/MTIME[6]} {wallypipelinedsoc/uncore/clint.clint/MTIME[7]} {wallypipelinedsoc/uncore/clint.clint/MTIME[8]} {wallypipelinedsoc/uncore/clint.clint/MTIME[9]} {wallypipelinedsoc/uncore/clint.clint/MTIME[10]} {wallypipelinedsoc/uncore/clint.clint/MTIME[11]} {wallypipelinedsoc/uncore/clint.clint/MTIME[12]} {wallypipelinedsoc/uncore/clint.clint/MTIME[13]} {wallypipelinedsoc/uncore/clint.clint/MTIME[14]} {wallypipelinedsoc/uncore/clint.clint/MTIME[15]} {wallypipelinedsoc/uncore/clint.clint/MTIME[16]} {wallypipelinedsoc/uncore/clint.clint/MTIME[17]} {wallypipelinedsoc/uncore/clint.clint/MTIME[18]} {wallypipelinedsoc/uncore/clint.clint/MTIME[19]} {wallypipelinedsoc/uncore/clint.clint/MTIME[20]} {wallypipelinedsoc/uncore/clint.clint/MTIME[21]} {wallypipelinedsoc/uncore/clint.clint/MTIME[22]} {wallypipelinedsoc/uncore/clint.clint/MTIME[23]} {wallypipelinedsoc/uncore/clint.clint/MTIME[24]} {wallypipelinedsoc/uncore/clint.clint/MTIME[25]} {wallypipelinedsoc/uncore/clint.clint/MTIME[26]} {wallypipelinedsoc/uncore/clint.clint/MTIME[27]} {wallypipelinedsoc/uncore/clint.clint/MTIME[28]} {wallypipelinedsoc/uncore/clint.clint/MTIME[29]} {wallypipelinedsoc/uncore/clint.clint/MTIME[30]} {wallypipelinedsoc/uncore/clint.clint/MTIME[31]} {wallypipelinedsoc/uncore/clint.clint/MTIME[32]} {wallypipelinedsoc/uncore/clint.clint/MTIME[33]} {wallypipelinedsoc/uncore/clint.clint/MTIME[34]} {wallypipelinedsoc/uncore/clint.clint/MTIME[35]} {wallypipelinedsoc/uncore/clint.clint/MTIME[36]} {wallypipelinedsoc/uncore/clint.clint/MTIME[37]} {wallypipelinedsoc/uncore/clint.clint/MTIME[38]} {wallypipelinedsoc/uncore/clint.clint/MTIME[39]} {wallypipelinedsoc/uncore/clint.clint/MTIME[40]} {wallypipelinedsoc/uncore/clint.clint/MTIME[41]} {wallypipelinedsoc/uncore/clint.clint/MTIME[42]} {wallypipelinedsoc/uncore/clint.clint/MTIME[43]} {wallypipelinedsoc/uncore/clint.clint/MTIME[44]} {wallypipelinedsoc/uncore/clint.clint/MTIME[45]} {wallypipelinedsoc/uncore/clint.clint/MTIME[46]} {wallypipelinedsoc/uncore/clint.clint/MTIME[47]} {wallypipelinedsoc/uncore/clint.clint/MTIME[48]} {wallypipelinedsoc/uncore/clint.clint/MTIME[49]} {wallypipelinedsoc/uncore/clint.clint/MTIME[50]} {wallypipelinedsoc/uncore/clint.clint/MTIME[51]} {wallypipelinedsoc/uncore/clint.clint/MTIME[52]} {wallypipelinedsoc/uncore/clint.clint/MTIME[53]} {wallypipelinedsoc/uncore/clint.clint/MTIME[54]} {wallypipelinedsoc/uncore/clint.clint/MTIME[55]} {wallypipelinedsoc/uncore/clint.clint/MTIME[56]} {wallypipelinedsoc/uncore/clint.clint/MTIME[57]} {wallypipelinedsoc/uncore/clint.clint/MTIME[58]} {wallypipelinedsoc/uncore/clint.clint/MTIME[59]} {wallypipelinedsoc/uncore/clint.clint/MTIME[60]} {wallypipelinedsoc/uncore/clint.clint/MTIME[61]} {wallypipelinedsoc/uncore/clint.clint/MTIME[62]} {wallypipelinedsoc/uncore/clint.clint/MTIME[63]} ]]
+
+
+
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe147]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe147]
+connect_debug_port u_ila_0/probe147 [get_nets [list {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[0]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[1]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[2]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[3]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[4]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[5]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[6]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[7]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[8]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[9]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[10]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[11]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[12]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[13]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[14]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[15]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[16]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[17]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[18]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[19]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[20]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[21]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[22]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[23]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[24]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[25]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[26]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[27]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[28]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[29]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[30]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[31]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[32]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[33]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[34]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[35]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[36]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[37]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[38]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[39]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[40]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[41]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[42]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[43]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[44]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[45]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[46]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[47]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[48]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[49]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[50]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[51]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[52]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[53]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[54]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[55]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[56]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[57]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[58]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[59]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[60]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[61]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[62]} {wallypipelinedsoc/uncore/clint.clint/MTIMECMP[63]} ]]
+
+
+
+create_debug_port u_ila_0 probe
+set_property port_width 12 [get_debug_ports u_ila_0/probe148]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe148]
+connect_debug_port u_ila_0/probe148 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[11]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe149]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe149]
+connect_debug_port u_ila_0/probe149 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[63]} ]]
diff --git a/fpga/generator/wave_config.wcfg b/fpga/generator/wave_config.wcfg
new file mode 100644
index 00000000..f98274f2
--- /dev/null
+++ b/fpga/generator/wave_config.wcfg
@@ -0,0 +1,495 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="/home/ross/repos/riscv-wally/fpga/generator/WallyFPGA.hw/hw_1/wave/hw_ila_data_1/hw_ila_data_1.wdb" id="1">
+         <top_modules>
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
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+         <obj_property name="Radix">HEXRADIX</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+      <wvobject type="logic" fp_name="wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/i_ERROR_CRC16">
+         <obj_property name="DisplayName">FullPathName</obj_property>
+         <obj_property name="ElementShortName">wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/i_ERROR_CRC16</obj_property>
+         <obj_property name="ObjectShortName">i_ERROR_CRC16</obj_property>
+         <obj_property name="LABELRADIX">true</obj_property>
+         <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+      </wvobject>
+   </wvobject>
+   <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[11:0]</obj_property>
+      <obj_property name="ObjectShortName">IP_REGW_writeable[11:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/csr/csri/MExtIntM">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csri/MExtIntM</obj_property>
+      <obj_property name="ObjectShortName">MExtIntM</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/csr/csri/SExtIntM">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csri/SExtIntM</obj_property>
+      <obj_property name="ObjectShortName">SExtIntM</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/csr/csri/SwIntM">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csri/SwIntM</obj_property>
+      <obj_property name="ObjectShortName">SwIntM</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/csr/csri/TimerIntM">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csri/TimerIntM</obj_property>
+      <obj_property name="ObjectShortName">TimerIntM</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[63:0]</obj_property>
+      <obj_property name="ObjectShortName">MEDELEG_REGW[63:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[11:0]</obj_property>
+      <obj_property name="ObjectShortName">MIDELEG_REGW[11:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="wallypipelinedsoc/uncore/clint.clint/MTIMECMP">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/uncore/clint.clint/MTIMECMP[63:0]</obj_property>
+      <obj_property name="ObjectShortName">MTIMECMP[63:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="wallypipelinedsoc/uncore/clint.clint/MTIME">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/uncore/clint.clint/MTIME[63:0]</obj_property>
+      <obj_property name="ObjectShortName">MTIME[63:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/intEn[1]__0">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[10:1]</obj_property>
+      <obj_property name="ObjectShortName">intEn[1]__0[10:1]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/intPriority[10]">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/intPriority[10][2:0]</obj_property>
+      <obj_property name="ObjectShortName">intPriority[10][2:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1]">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][10:1]</obj_property>
+      <obj_property name="ObjectShortName">irqMatrix[1][1][10:1]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2]">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][10:1]</obj_property>
+      <obj_property name="ObjectShortName">irqMatrix[1][2][10:1]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3]">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][10:1]</obj_property>
+      <obj_property name="ObjectShortName">irqMatrix[1][3][10:1]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4]">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][10:1]</obj_property>
+      <obj_property name="ObjectShortName">irqMatrix[1][4][10:1]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5]">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][10:1]</obj_property>
+      <obj_property name="ObjectShortName">irqMatrix[1][5][10:1]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6]">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][10:1]</obj_property>
+      <obj_property name="ObjectShortName">irqMatrix[1][6][10:1]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7]">
+      <obj_property name="DisplayName">FullPathName</obj_property>
+      <obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][10:1]</obj_property>
+      <obj_property name="ObjectShortName">irqMatrix[1][7][10:1]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+      <obj_property name="LABELRADIX">true</obj_property>
+      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
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+</wave_config>
diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh
index 56ca71c9..a7e94081 100644
--- a/pipelined/config/fpga/wally-config.vh
+++ b/pipelined/config/fpga/wally-config.vh
@@ -42,6 +42,7 @@
 `define ZIFENCEI_SUPPORTED 1
 `define ZICOUNTERS_SUPPORTED 1
 `define COUNTERS 32
+`define DESIGN_COMPILER 0
 
 // Microarchitectural Features
 `define UARCH_PIPELINED 1
diff --git a/pipelined/config/rv32ia/BTBPredictor.txt b/pipelined/config/rv32ia/BTBPredictor.txt
new file mode 100644
index 00000000..fd3eedff
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+++ b/pipelined/config/rv32ia/BTBPredictor.txt
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diff --git a/pipelined/config/rv32ia/twoBitPredictor.txt b/pipelined/config/rv32ia/twoBitPredictor.txt
new file mode 100644
index 00000000..ff57bd47
--- /dev/null
+++ b/pipelined/config/rv32ia/twoBitPredictor.txt
@@ -0,0 +1,1024 @@
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diff --git a/pipelined/config/rv32ia/wally-config.vh b/pipelined/config/rv32ia/wally-config.vh
new file mode 100644
index 00000000..93dda4a6
--- /dev/null
+++ b/pipelined/config/rv32ia/wally-config.vh
@@ -0,0 +1,135 @@
+//////////////////////////////////////////
+// wally-config.vh
+//
+// Written: David_Harris@hmc.edu 4 January 2021
+// Modified: 
+//
+// Purpose: Specify which features are configured
+//          Macros to determine which modes are supported based on MISA
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+// include shared configuration
+`include "wally-shared.vh"
+
+`define FPGA 0
+`define QEMU 0
+`define DESIGN_COMPILER 0
+
+// RV32 or RV64: XLEN = 32 or 64
+`define XLEN 32
+
+// IEEE 754 compliance
+`define IEEE754 0
+
+// IA
+`define MISA (32'h00000100 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0 | 1 << 3 | 1 << 5)
+`define ZICSR_SUPPORTED 1
+`define ZIFENCEI_SUPPORTED 1
+`define COUNTERS 32
+`define ZICOUNTERS_SUPPORTED 1
+
+// Microarchitectural Features
+`define UARCH_PIPELINED 1
+`define UARCH_SUPERSCALR 0
+`define UARCH_SINGLECYCLE 0
+// *** replace with MEM_BUS
+`define DMEM `MEM_CACHE
+`define IMEM `MEM_CACHE
+`define DBUS 1
+`define IBUS 1
+`define VIRTMEM_SUPPORTED 1
+`define VECTORED_INTERRUPTS_SUPPORTED 1 
+
+// TLB configuration.  Entries should be a power of 2
+`define ITLB_ENTRIES 32
+`define DTLB_ENTRIES 32
+
+// Cache configuration.  Sizes should be a power of two
+// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
+`define DCACHE_NUMWAYS 4
+`define DCACHE_WAYSIZEINBYTES 4096
+`define DCACHE_LINELENINBITS 256
+`define ICACHE_NUMWAYS 4
+`define ICACHE_WAYSIZEINBYTES 4096
+`define ICACHE_LINELENINBITS 256
+
+// Integer Divider Configuration
+// DIV_BITSPERCYCLE must be 1, 2, or 4
+`define DIV_BITSPERCYCLE 4
+
+// Legal number of PMP entries are 0, 16, or 64
+`define PMP_ENTRIES 64
+
+// Address space
+`define RESET_VECTOR 32'h80000000
+
+// Peripheral Addresses
+// Peripheral memory space extends from BASE to BASE+RANGE
+// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
+`define BOOTROM_SUPPORTED 1'b1
+`define BOOTROM_BASE   34'h00001000 
+`define BOOTROM_RANGE  34'h00000FFF
+`define RAM_SUPPORTED 1'b1
+`define RAM_BASE       34'h80000000
+`define RAM_RANGE      34'h07FFFFFF
+`define EXT_MEM_SUPPORTED 1'b0
+`define EXT_MEM_BASE       34'h80000000
+`define EXT_MEM_RANGE      34'h07FFFFFF
+`define CLINT_SUPPORTED 1'b0
+`define CLINT_BASE  34'h02000000
+`define CLINT_RANGE 34'h0000FFFF
+`define GPIO_SUPPORTED 1'b0
+`define GPIO_BASE   34'h10060000
+`define GPIO_RANGE  34'h000000FF
+`define UART_SUPPORTED 1'b1
+`define UART_BASE   34'h10000000
+`define UART_RANGE  34'h00000007
+`define PLIC_SUPPORTED 1'b1
+`define PLIC_BASE   34'h0C000000
+`define PLIC_RANGE  34'h03FFFFFF
+`define SDC_SUPPORTED 1'b0
+`define SDC_BASE   34'h00012100
+`define SDC_RANGE  34'h0000001F
+
+// Bus Interface width
+`define AHBW 32
+
+// Test modes
+
+// Tie GPIO outputs back to inputs
+`define GPIO_LOOPBACK_TEST 1
+
+// Hardware configuration
+`define UART_PRESCALE 1
+
+// Interrupt configuration
+`define PLIC_NUM_SRC 10 
+// comment out the following if >=32 sources
+`define PLIC_NUM_SRC_LT_32
+`define PLIC_GPIO_ID 3
+`define PLIC_UART_ID 10
+
+`define TWO_BIT_PRELOAD "../config/rv32ia/twoBitPredictor.txt"
+`define BTB_PRELOAD "../config/rv32ia/BTBPredictor.txt"
+`define BPRED_ENABLED 1
+`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
+`define TESTSBP 0
+
+`define REPLAY 0
+`define HPTW_WRITES_SUPPORTED 0
diff --git a/pipelined/config/rv64ia/BTBPredictor.txt b/pipelined/config/rv64ia/BTBPredictor.txt
new file mode 100644
index 00000000..b761147c
--- /dev/null
+++ b/pipelined/config/rv64ia/BTBPredictor.txt
@@ -0,0 +1,1024 @@
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diff --git a/pipelined/config/rv64ia/wally-config.vh b/pipelined/config/rv64ia/wally-config.vh
new file mode 100644
index 00000000..efe101c2
--- /dev/null
+++ b/pipelined/config/rv64ia/wally-config.vh
@@ -0,0 +1,136 @@
+//////////////////////////////////////////
+// wally-config.vh
+//
+// Written: David_Harris@hmc.edu 4 January 2021
+// Modified: 
+//
+// Purpose: Specify which features are configured
+//          Macros to determine which modes are supported based on MISA
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+// include shared configuration
+`include "wally-shared.vh"
+
+`define FPGA 0
+`define QEMU 0
+`define DESIGN_COMPILER 0
+
+// RV32 or RV64: XLEN = 32 or 64
+`define XLEN 64
+
+// IEEE 754 compliance
+`define IEEE754 0
+
+// MISA RISC-V configuration per specification IA
+`define MISA (32'h00000100 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0 | 1 << 3 | 1 << 5)
+`define ZICSR_SUPPORTED 1
+`define ZIFENCEI_SUPPORTED 1
+`define COUNTERS 32
+`define ZICOUNTERS_SUPPORTED 1
+
+/// Microarchitectural Features
+`define UARCH_PIPELINED 1
+`define UARCH_SUPERSCALR 0
+`define UARCH_SINGLECYCLE 0
+`define DMEM `MEM_CACHE
+`define IMEM `MEM_CACHE
+`define DBUS 1
+`define IBUS 1
+`define VIRTMEM_SUPPORTED 1
+`define VECTORED_INTERRUPTS_SUPPORTED 1 
+
+// TLB configuration.  Entries should be a power of 2
+`define ITLB_ENTRIES 32
+`define DTLB_ENTRIES 32
+
+// Cache configuration.  Sizes should be a power of two
+// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
+`define DCACHE_NUMWAYS 4
+`define DCACHE_WAYSIZEINBYTES 4096
+`define DCACHE_LINELENINBITS 256
+`define ICACHE_NUMWAYS 4
+`define ICACHE_WAYSIZEINBYTES 4096
+`define ICACHE_LINELENINBITS 256
+
+// Integer Divider Configuration
+// DIV_BITSPERCYCLE must be 1, 2, or 4
+`define DIV_BITSPERCYCLE 4
+
+// Legal number of PMP entries are 0, 16, or 64
+`define PMP_ENTRIES 64
+
+// Address space
+`define RESET_VECTOR 64'h0000000080000000
+
+// Bus Interface width
+`define AHBW 64
+
+// Peripheral Physiccal Addresses
+// Peripheral memory space extends from BASE to BASE+RANGE
+// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
+
+// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
+`define BOOTROM_SUPPORTED 1'b1
+`define BOOTROM_BASE   56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
+`define BOOTROM_RANGE  56'h00000FFF
+`define RAM_SUPPORTED 1'b1
+`define RAM_BASE       56'h80000000
+`define RAM_RANGE      56'h7FFFFFFF
+`define EXT_MEM_SUPPORTED 1'b0
+`define EXT_MEM_BASE       56'h80000000
+`define EXT_MEM_RANGE      56'h07FFFFFF
+`define CLINT_SUPPORTED 1'b1
+`define CLINT_BASE  56'h02000000
+`define CLINT_RANGE 56'h0000FFFF
+`define GPIO_SUPPORTED 1'b1
+`define GPIO_BASE   56'h10060000
+`define GPIO_RANGE  56'h000000FF
+`define UART_SUPPORTED 1'b1
+`define UART_BASE   56'h10000000
+`define UART_RANGE  56'h00000007
+`define PLIC_SUPPORTED 1'b1
+`define PLIC_BASE   56'h0C000000
+`define PLIC_RANGE  56'h03FFFFFF
+`define SDC_SUPPORTED 1'b0
+`define SDC_BASE   56'h00012100
+`define SDC_RANGE  56'h0000001F
+
+// Test modes
+
+// Tie GPIO outputs back to inputs
+`define GPIO_LOOPBACK_TEST 1
+
+// Hardware configuration
+`define UART_PRESCALE 1
+
+// Interrupt configuration
+`define PLIC_NUM_SRC 10
+// comment out the following if >=32 sources
+`define PLIC_NUM_SRC_LT_32
+`define PLIC_GPIO_ID 3
+`define PLIC_UART_ID 10
+
+`define TWO_BIT_PRELOAD "../config/rv64ia/twoBitPredictor.txt"
+`define BTB_PRELOAD "../config/rv64ia/BTBPredictor.txt"
+`define BPRED_ENABLED 1
+`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
+`define TESTSBP 0
+
+`define REPLAY 0
+`define HPTW_WRITES_SUPPORTED 0
diff --git a/pipelined/regression/fpga-wave.do b/pipelined/regression/fpga-wave.do
index e95321f5..51046eb7 100644
--- a/pipelined/regression/fpga-wave.do
+++ b/pipelined/regression/fpga-wave.do
@@ -2,578 +2,517 @@ onerror {resume}
 quietly WaveActivateNextPane {} 0
 add wave -noupdate /testbench/clk
 add wave -noupdate /testbench/reset
-add wave -noupdate /testbench/test
+add wave -noupdate /testbench/reset_ext
 add wave -noupdate /testbench/memfilename
-add wave -noupdate /testbench/dut/wallypipelinedsoc/core/SATP_REGW
-add wave -noupdate -expand -group {Execution Stage} /testbench/dut/wallypipelinedsoc/core/ifu/PCE
-add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
-add wave -noupdate -expand -group {Execution Stage} /testbench/dut/wallypipelinedsoc/core/ifu/InstrE
-add wave -noupdate -expand -group {Memory Stage} /testbench/dut/wallypipelinedsoc/core/priv/trap/InstrValidM
-add wave -noupdate -expand -group {Memory Stage} /testbench/dut/wallypipelinedsoc/core/PCM
-add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
-add wave -noupdate -expand -group {Memory Stage} /testbench/dut/wallypipelinedsoc/core/InstrM
-add wave -noupdate -expand -group {Memory Stage} /testbench/dut/wallypipelinedsoc/core/lsu/MemAdrM
-add wave -noupdate /testbench/dut/wallypipelinedsoc/core/ieu/dp/ResultM
-add wave -noupdate /testbench/dut/wallypipelinedsoc/core/ieu/dp/ResultW
-add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/core/priv/trap/InstrMisalignedFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/core/priv/trap/InstrAccessFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/core/priv/trap/IllegalInstrFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/core/priv/trap/BreakpointFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/core/priv/trap/LoadMisalignedFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/core/priv/trap/StoreAmoMisalignedFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/core/priv/trap/LoadAccessFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/core/priv/trap/StoreAmoAccessFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/core/priv/trap/EcallFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/core/priv/trap/InstrPageFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/core/priv/trap/LoadPageFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/core/priv/trap/StorePageFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/wallypipelinedsoc/core/priv/trap/InterruptM
-add wave -noupdate -group HDU -group interrupts /testbench/dut/wallypipelinedsoc/core/priv/trap/PendingIntsM
-add wave -noupdate -group HDU -group interrupts /testbench/dut/wallypipelinedsoc/core/priv/trap/CommittedM
-add wave -noupdate -group HDU -group interrupts /testbench/dut/wallypipelinedsoc/core/priv/trap/InstrValidM
-add wave -noupdate -group HDU -group hazards /testbench/dut/wallypipelinedsoc/core/hzu/BPPredWrongE
-add wave -noupdate -group HDU -group hazards /testbench/dut/wallypipelinedsoc/core/hzu/CSRWritePendingDEM
-add wave -noupdate -group HDU -group hazards /testbench/dut/wallypipelinedsoc/core/hzu/RetM
-add wave -noupdate -group HDU -group hazards /testbench/dut/wallypipelinedsoc/core/hzu/TrapM
-add wave -noupdate -group HDU -group hazards /testbench/dut/wallypipelinedsoc/core/hzu/LoadStallD
-add wave -noupdate -group HDU -group hazards /testbench/dut/wallypipelinedsoc/core/hzu/StoreStallD
-add wave -noupdate -group HDU -group hazards /testbench/dut/wallypipelinedsoc/core/hzu/ICacheStallF
-add wave -noupdate -group HDU -group hazards /testbench/dut/wallypipelinedsoc/core/hzu/LSUStallM
-add wave -noupdate -group HDU -group hazards /testbench/dut/wallypipelinedsoc/core/MulDivStallD
-add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/wallypipelinedsoc/core/hzu/FlushF
-add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/wallypipelinedsoc/core/FlushD
-add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/wallypipelinedsoc/core/FlushE
-add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/wallypipelinedsoc/core/FlushM
-add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/wallypipelinedsoc/core/FlushW
-add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/wallypipelinedsoc/core/StallF
-add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/wallypipelinedsoc/core/StallD
-add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/wallypipelinedsoc/core/StallE
-add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/wallypipelinedsoc/core/StallM
-add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/wallypipelinedsoc/core/StallW
-add wave -noupdate -group Bpred -color Orange /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/GHR
-add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
-add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
-add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/BPInstrClassE[0]}
-add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/BPPredDirWrongE
-add wave -noupdate -group Bpred -expand -group {branch update selection inputs} -divider {class check}
-add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightNonCFI
-add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongCFI
-add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongNonCFI
-add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPRight
-add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPWrong
-add wave -noupdate -group Bpred -radix hexadecimal -childformat {{{/testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} -radix binary} {{/testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} -radix binary} {{/testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} -radix binary} {{/testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} -radix binary} {{/testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} -radix binary} {{/testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} -radix binary} {{/testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} -radix binary}} -subitemconfig {{/testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} {-height 16 -radix binary} {/testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} {-height 16 -radix binary} {/testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} {-height 16 -radix binary} {/testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} {-height 16 -radix binary} {/testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} {-height 16 -radix binary} {/testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} {-height 16 -radix binary} {/testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} {-height 16 -radix binary}} /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel
-add wave -noupdate -group Bpred /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNext
-add wave -noupdate -group Bpred /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRUpdateEN
-add wave -noupdate -group Bpred /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr
-add wave -noupdate -group Bpred /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr0
-add wave -noupdate -group Bpred /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr1
-add wave -noupdate -group Bpred /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateEN
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRLookup
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/PCNextF
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/PHT/RA1
-add wave -noupdate -group Bpred -expand -group prediction -radix binary /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/BPPredF
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/BTBValidF
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/BPInstrClassF
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/BTBPredPCF
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/RASPCF
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/TargetPredictor/LookUpPCIndex
-add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/TargetPredictor/TargetPC
-add wave -noupdate -group Bpred -expand -group prediction -expand -group ex -radix binary /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/BPPredE
-add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/PCSrcE
-add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/BPPredDirWrongE
-add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/TargetPredictor/UpdatePCIndex
-add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/TargetPredictor/UpdateTarget
-add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/TargetPredictor/UpdateEN
-add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/TargetPredictor/UpdatePC
-add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/TargetPredictor/UpdateTarget
-add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr
-add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/PCE
-add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/Predictor/DirPredictor/PHT/WA1
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/TargetWrongE
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/FallThroughWrongE
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/PredictionPCWrongE
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/InstrClassE
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/PredictionInstrClassWrongE
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/BPPredClassNonCFIWrongE
-add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/BPPredWrongE
-add wave -noupdate -group Bpred /testbench/dut/wallypipelinedsoc/core/ifu/bpred/bpred/BPPredWrongE
+add wave -noupdate /testbench/dut/core/SATP_REGW
+add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/BPPredWrongE
+add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/CSRWritePendingDEM
+add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/RetM
+add wave -noupdate -group HDU -group hazards -color Pink /testbench/dut/core/hzu/TrapM
+add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/LoadStallD
+add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/StoreStallD
+add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/LSUStallM
+add wave -noupdate -group HDU -group hazards /testbench/dut/core/MDUStallD
+add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/DivBusyE
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InterruptM
+add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/hzu/FlushF
+add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD
+add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE
+add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM
+add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW
+add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallF
+add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallD
+add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallE
+add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallM
+add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallW
 add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
-add wave -noupdate -group {instruction pipeline} /testbench/dut/wallypipelinedsoc/core/ifu/bus/icache/FinalInstrRawF
-add wave -noupdate -group {instruction pipeline} /testbench/dut/wallypipelinedsoc/core/ifu/InstrD
-add wave -noupdate -group {instruction pipeline} /testbench/dut/wallypipelinedsoc/core/ifu/InstrE
-add wave -noupdate -group {instruction pipeline} /testbench/dut/wallypipelinedsoc/core/ifu/InstrM
-add wave -noupdate -group {instruction pipeline} /testbench/InstrW
-add wave -noupdate -group {PCNext Generation} /testbench/dut/wallypipelinedsoc/core/ifu/PCNextF
-add wave -noupdate -group {PCNext Generation} /testbench/dut/wallypipelinedsoc/core/ifu/PCF
-add wave -noupdate -group {PCNext Generation} /testbench/dut/wallypipelinedsoc/core/ifu/PCPlus2or4F
-add wave -noupdate -group {PCNext Generation} /testbench/dut/wallypipelinedsoc/core/ifu/BPPredPCF
-add wave -noupdate -group {PCNext Generation} /testbench/dut/wallypipelinedsoc/core/ifu/PCNext0F
-add wave -noupdate -group {PCNext Generation} /testbench/dut/wallypipelinedsoc/core/ifu/PCNext1F
-add wave -noupdate -group {PCNext Generation} /testbench/dut/wallypipelinedsoc/core/ifu/SelBPPredF
-add wave -noupdate -group {PCNext Generation} /testbench/dut/wallypipelinedsoc/core/ifu/BPPredWrongE
-add wave -noupdate -group {PCNext Generation} /testbench/dut/wallypipelinedsoc/core/ifu/PrivilegedChangePCM
-add wave -noupdate -group {Decode Stage} /testbench/dut/wallypipelinedsoc/core/ifu/InstrD
+add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/FinalInstrRawF
+add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
+add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrE
+add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrM
+add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/PCD
+add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/InstrD
 add wave -noupdate -group {Decode Stage} /testbench/InstrDName
-add wave -noupdate -group {Decode Stage} /testbench/dut/wallypipelinedsoc/core/ieu/c/RegWriteD
-add wave -noupdate -group {Decode Stage} /testbench/dut/wallypipelinedsoc/core/ieu/dp/RdD
-add wave -noupdate -group {Decode Stage} /testbench/dut/wallypipelinedsoc/core/ieu/dp/Rs1D
-add wave -noupdate -group {Decode Stage} /testbench/dut/wallypipelinedsoc/core/ieu/dp/Rs2D
-add wave -noupdate -group RegFile -expand /testbench/dut/wallypipelinedsoc/core/ieu/dp/regf/rf
-add wave -noupdate -group RegFile /testbench/dut/wallypipelinedsoc/core/ieu/dp/regf/a1
-add wave -noupdate -group RegFile /testbench/dut/wallypipelinedsoc/core/ieu/dp/regf/a2
-add wave -noupdate -group RegFile /testbench/dut/wallypipelinedsoc/core/ieu/dp/regf/a3
-add wave -noupdate -group RegFile /testbench/dut/wallypipelinedsoc/core/ieu/dp/regf/rd1
-add wave -noupdate -group RegFile /testbench/dut/wallypipelinedsoc/core/ieu/dp/regf/rd2
-add wave -noupdate -group RegFile /testbench/dut/wallypipelinedsoc/core/ieu/dp/regf/we3
-add wave -noupdate -group RegFile /testbench/dut/wallypipelinedsoc/core/ieu/dp/regf/wd3
-add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/wallypipelinedsoc/core/ieu/dp/IntResultW
-add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/wallypipelinedsoc/core/ieu/dp/ReadDataW
-add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/wallypipelinedsoc/core/ieu/dp/CSRReadValW
-add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/wallypipelinedsoc/core/ieu/dp/ResultSrcW
-add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/wallypipelinedsoc/core/ieu/dp/ResultW
-add wave -noupdate -group alu /testbench/dut/wallypipelinedsoc/core/ieu/dp/alu/A
-add wave -noupdate -group alu /testbench/dut/wallypipelinedsoc/core/ieu/dp/alu/B
-add wave -noupdate -group alu /testbench/dut/wallypipelinedsoc/core/ieu/dp/alu/ALUControl
-add wave -noupdate -group alu /testbench/dut/wallypipelinedsoc/core/ieu/dp/alu/result
-add wave -noupdate -group alu /testbench/dut/wallypipelinedsoc/core/ieu/dp/alu/FlagsEEEEE
-add wave -noupdate -group alu -divider internals
-add wave -noupdate -group Forward /testbench/dut/wallypipelinedsoc/core/ieu/fw/Rs1D
-add wave -noupdate -group Forward /testbench/dut/wallypipelinedsoc/core/ieu/fw/Rs2D
-add wave -noupdate -group Forward /testbench/dut/wallypipelinedsoc/core/ieu/fw/Rs1E
-add wave -noupdate -group Forward /testbench/dut/wallypipelinedsoc/core/ieu/fw/Rs2E
-add wave -noupdate -group Forward /testbench/dut/wallypipelinedsoc/core/ieu/fw/RdE
-add wave -noupdate -group Forward /testbench/dut/wallypipelinedsoc/core/ieu/fw/RdM
-add wave -noupdate -group Forward /testbench/dut/wallypipelinedsoc/core/ieu/fw/RdW
-add wave -noupdate -group Forward /testbench/dut/wallypipelinedsoc/core/ieu/fw/MemReadE
-add wave -noupdate -group Forward /testbench/dut/wallypipelinedsoc/core/ieu/fw/RegWriteM
-add wave -noupdate -group Forward /testbench/dut/wallypipelinedsoc/core/ieu/fw/RegWriteW
-add wave -noupdate -group Forward -color Thistle /testbench/dut/wallypipelinedsoc/core/ieu/fw/ForwardAE
-add wave -noupdate -group Forward -color Thistle /testbench/dut/wallypipelinedsoc/core/ieu/fw/ForwardBE
-add wave -noupdate -group Forward -color Thistle /testbench/dut/wallypipelinedsoc/core/ieu/fw/LoadStallD
-add wave -noupdate -group {alu execution stage} /testbench/dut/wallypipelinedsoc/core/ieu/dp/WriteDataE
-add wave -noupdate -group {alu execution stage} /testbench/dut/wallypipelinedsoc/core/ieu/dp/ALUResultE
-add wave -noupdate -group {alu execution stage} /testbench/dut/wallypipelinedsoc/core/ieu/dp/SrcAE
-add wave -noupdate -group {alu execution stage} /testbench/dut/wallypipelinedsoc/core/ieu/dp/SrcBE
-add wave -noupdate -group PCS /testbench/dut/wallypipelinedsoc/core/ifu/PCNextF
-add wave -noupdate -group PCS /testbench/dut/wallypipelinedsoc/core/PCF
-add wave -noupdate -group PCS /testbench/dut/wallypipelinedsoc/core/ifu/PCD
-add wave -noupdate -group PCS /testbench/dut/wallypipelinedsoc/core/PCE
-add wave -noupdate -group PCS /testbench/dut/wallypipelinedsoc/core/PCM
+add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/InstrValidD
+add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/RegWriteD
+add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/RdD
+add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs1D
+add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs2D
+add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/PCE
+add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/InstrE
+add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
+add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE
+add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName
+add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM
+add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM
+add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
+add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM
+add wave -noupdate -group {WriteBack stage} /testbench/PCW
+add wave -noupdate -group {WriteBack stage} /testbench/InstrW
+add wave -noupdate -group {WriteBack stage} /testbench/InstrWName
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTEREN_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTINHIBIT_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MEDELEG_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MEPC_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIDELEG_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIE_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIP_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MSTATUS_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MTVEC_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/PMPADDR_ARRAY_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/PMPCFG_ARRAY_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SATP_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SCOUNTEREN_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SEPC_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SIE_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SIP_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW
+add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW
+add wave -noupdate -group Bpred -color Orange /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHR
+add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
+add wave -noupdate -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
+add wave -noupdate -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPInstrClassE[0]}
+add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPPredDirWrongE
+add wave -noupdate -group Bpred -group {branch update selection inputs} -divider {class check}
+add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightNonCFI
+add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongCFI
+add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongNonCFI
+add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPRight
+add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPWrong
+add wave -noupdate -group Bpred -radix hexadecimal -childformat {{{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} -radix binary}} -subitemconfig {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} {-height 16 -radix binary}} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel
+add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNext
+add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRUpdateEN
+add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr
+add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr0
+add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr1
+add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateEN
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRLookup
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCNextF
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHT/RA1
+add wave -noupdate -group Bpred -expand -group prediction -radix binary /testbench/dut/core/ifu/bpred/bpred/BPPredF
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBValidF
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BPInstrClassF
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBPredPCF
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/LookUpPCIndex
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/TargetPC
+add wave -noupdate -group Bpred -expand -group prediction -expand -group ex -radix binary /testbench/dut/core/ifu/bpred/bpred/BPPredE
+add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
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+add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdatePCIndex
+add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateTarget
+add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateEN
+add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdatePC
+add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateTarget
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+add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHT/WA1
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+add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
+add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
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+add wave -noupdate -group PCS /testbench/dut/core/PCF
+add wave -noupdate -group PCS /testbench/dut/core/ifu/PCD
+add wave -noupdate -group PCS /testbench/dut/core/PCE
+add wave -noupdate -group PCS /testbench/dut/core/PCM
 add wave -noupdate -group PCS /testbench/PCW
-add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/core/mdu/InstrD
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-add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/core/mdu/ForwardedSrcBE
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-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/word[0]/CacheDataMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/word[1]/CacheDataMem/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/word[1]/CacheDataMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/word[2]/CacheDataMem/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/word[2]/CacheDataMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/word[3]/CacheDataMem/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[1]/word[3]/CacheDataMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/SetValid}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/SetDirty}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/CacheTagMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/DirtyBits}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/ValidBits}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/word[0]/CacheDataMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/word[0]/CacheDataMem/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/word[1]/CacheDataMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/word[1]/CacheDataMem/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/word[2]/CacheDataMem/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/word[2]/CacheDataMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/word[3]/CacheDataMem/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[2]/word[3]/CacheDataMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/SetValid}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/SetDirty}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/CacheTagMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/DirtyBits}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/ValidBits}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/word[0]/CacheDataMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/word[0]/CacheDataMem/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/word[1]/CacheDataMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/word[1]/CacheDataMem/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/word[2]/CacheDataMem/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/word[2]/CacheDataMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/word[3]/CacheDataMem/WriteEnable}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[3]/word[3]/CacheDataMem/StoredData}
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/SetValid
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/ClearValid
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/SetDirty
-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/ClearDirty
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-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheWays[0]/Dirty}
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-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/ReadDataBlockWayMaskedM
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-add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/ReadDataWordMuxM
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-add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/VictimWay
-add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/VictimDirtyWay
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-add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/CacheHit
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-add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/FetchCountFlag
-add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/AHBPAdr
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-add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/HWDATA
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-add wave -noupdate -group lsu -group dtlb /testbench/dut/wallypipelinedsoc/core/lsu/dmmu/TLBHit
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-add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/wallypipelinedsoc/core/lsu/dmmu/LoadAccessFaultM
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-add wave -noupdate -group lsu -group pma /testbench/dut/wallypipelinedsoc/core/lsu/dmmu/PMAStoreAmoAccessFaultM
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-add wave -noupdate -group lsu -group pmp /testbench/dut/wallypipelinedsoc/core/lsu/dmmu/PMPStoreAmoAccessFaultM
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-add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/wallypipelinedsoc/core/lsu/hptw/WalkerStorePageFaultM
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-add wave -noupdate /testbench/dut/wallypipelinedsoc/core/lsu.bus.dcache/MemPAdrM
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-add wave -noupdate -group plic /testbench/dut/wallypipelinedsoc/uncore/plic/plic/HADDR
-add wave -noupdate -group plic /testbench/dut/wallypipelinedsoc/uncore/plic/plic/HWRITE
-add wave -noupdate -group plic /testbench/dut/wallypipelinedsoc/uncore/plic/plic/HREADY
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-add wave -noupdate -group plic /testbench/dut/wallypipelinedsoc/uncore/plic/plic/HWDATA
-add wave -noupdate -group plic /testbench/dut/wallypipelinedsoc/uncore/plic/plic/UARTIntr
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-add wave -noupdate -group plic /testbench/dut/wallypipelinedsoc/uncore/plic/plic/HREADPLIC
-add wave -noupdate -group plic /testbench/dut/wallypipelinedsoc/uncore/plic/plic/HRESPPLIC
-add wave -noupdate -group plic /testbench/dut/wallypipelinedsoc/uncore/plic/plic/HREADYPLIC
-add wave -noupdate -group plic /testbench/dut/wallypipelinedsoc/uncore/plic/plic/ExtIntM
-add wave -noupdate -group GPIO /testbench/dut/wallypipelinedsoc/uncore/gpio/gpio/HCLK
-add wave -noupdate -group GPIO /testbench/dut/wallypipelinedsoc/uncore/gpio/gpio/HSELGPIO
-add wave -noupdate -group GPIO /testbench/dut/wallypipelinedsoc/uncore/gpio/gpio/HADDR
-add wave -noupdate -group GPIO /testbench/dut/wallypipelinedsoc/uncore/gpio/gpio/HWDATA
-add wave -noupdate -group GPIO /testbench/dut/wallypipelinedsoc/uncore/gpio/gpio/HWRITE
-add wave -noupdate -group GPIO /testbench/dut/wallypipelinedsoc/uncore/gpio/gpio/HREADY
-add wave -noupdate -group GPIO /testbench/dut/wallypipelinedsoc/uncore/gpio/gpio/HTRANS
-add wave -noupdate -group GPIO /testbench/dut/wallypipelinedsoc/uncore/gpio/gpio/HREADGPIO
-add wave -noupdate -group GPIO /testbench/dut/wallypipelinedsoc/uncore/gpio/gpio/HRESPGPIO
-add wave -noupdate -group GPIO /testbench/dut/wallypipelinedsoc/uncore/gpio/gpio/HREADYGPIO
-add wave -noupdate -group GPIO /testbench/dut/wallypipelinedsoc/uncore/gpio/gpio/GPIOPinsIn
-add wave -noupdate -group GPIO /testbench/dut/wallypipelinedsoc/uncore/gpio/gpio/GPIOPinsOut
-add wave -noupdate -group GPIO /testbench/dut/wallypipelinedsoc/uncore/gpio/gpio/GPIOPinsEn
-add wave -noupdate -group GPIO /testbench/dut/wallypipelinedsoc/uncore/gpio/gpio/GPIOIntr
-add wave -noupdate -group CLINT /testbench/dut/wallypipelinedsoc/uncore/clint/clint/HCLK
-add wave -noupdate -group CLINT /testbench/dut/wallypipelinedsoc/uncore/clint/clint/HSELCLINT
-add wave -noupdate -group CLINT /testbench/dut/wallypipelinedsoc/uncore/clint/clint/HADDR
-add wave -noupdate -group CLINT /testbench/dut/wallypipelinedsoc/uncore/clint/clint/HWRITE
-add wave -noupdate -group CLINT /testbench/dut/wallypipelinedsoc/uncore/clint/clint/HWDATA
-add wave -noupdate -group CLINT /testbench/dut/wallypipelinedsoc/uncore/clint/clint/HREADY
-add wave -noupdate -group CLINT /testbench/dut/wallypipelinedsoc/uncore/clint/clint/HTRANS
-add wave -noupdate -group CLINT /testbench/dut/wallypipelinedsoc/uncore/clint/clint/HREADCLINT
-add wave -noupdate -group CLINT /testbench/dut/wallypipelinedsoc/uncore/clint/clint/HRESPCLINT
-add wave -noupdate -group CLINT /testbench/dut/wallypipelinedsoc/uncore/clint/clint/HREADYCLINT
-add wave -noupdate -group CLINT /testbench/dut/wallypipelinedsoc/uncore/clint/clint/MTIME
-add wave -noupdate -group CLINT /testbench/dut/wallypipelinedsoc/uncore/clint/clint/MTIMECMP
-add wave -noupdate -group CLINT /testbench/dut/wallypipelinedsoc/uncore/clint/clint/TimerIntM
-add wave -noupdate -group CLINT /testbench/dut/wallypipelinedsoc/uncore/clint/clint/SwIntM
-add wave -noupdate -group uart /testbench/dut/wallypipelinedsoc/uncore/uart/uart/HCLK
-add wave -noupdate -group uart /testbench/dut/wallypipelinedsoc/uncore/uart/uart/HRESETn
-add wave -noupdate -group uart /testbench/dut/wallypipelinedsoc/uncore/uart/uart/HSELUART
-add wave -noupdate -group uart /testbench/dut/wallypipelinedsoc/uncore/uart/uart/HADDR
-add wave -noupdate -group uart /testbench/dut/wallypipelinedsoc/uncore/uart/uart/HWRITE
-add wave -noupdate -group uart /testbench/dut/wallypipelinedsoc/uncore/uart/uart/HWDATA
-add wave -noupdate -group uart /testbench/dut/wallypipelinedsoc/uncore/uart/uart/HREADUART
-add wave -noupdate -group uart /testbench/dut/wallypipelinedsoc/uncore/uart/uart/HRESPUART
-add wave -noupdate -group uart /testbench/dut/wallypipelinedsoc/uncore/uart/uart/HREADYUART
-add wave -noupdate -group uart /testbench/dut/wallypipelinedsoc/uncore/uart/uart/SIN
-add wave -noupdate -group uart /testbench/dut/wallypipelinedsoc/uncore/uart/uart/DSRb
-add wave -noupdate -group uart /testbench/dut/wallypipelinedsoc/uncore/uart/uart/DCDb
-add wave -noupdate -group uart /testbench/dut/wallypipelinedsoc/uncore/uart/uart/CTSb
-add wave -noupdate -group uart /testbench/dut/wallypipelinedsoc/uncore/uart/uart/RIb
-add wave -noupdate -group uart -expand -group outputs /testbench/dut/wallypipelinedsoc/uncore/uart/uart/SOUT
-add wave -noupdate -group uart -expand -group outputs /testbench/dut/wallypipelinedsoc/uncore/uart/uart/RTSb
-add wave -noupdate -group uart -expand -group outputs /testbench/dut/wallypipelinedsoc/uncore/uart/uart/DTRb
-add wave -noupdate -group uart -expand -group outputs /testbench/dut/wallypipelinedsoc/uncore/uart/uart/OUT1b
-add wave -noupdate -group uart -expand -group outputs /testbench/dut/wallypipelinedsoc/uncore/uart/uart/OUT2b
-add wave -noupdate -group uart -expand -group outputs /testbench/dut/wallypipelinedsoc/uncore/uart/uart/INTR
-add wave -noupdate -group uart -expand -group outputs /testbench/dut/wallypipelinedsoc/uncore/uart/uart/TXRDYb
-add wave -noupdate -group uart -expand -group outputs /testbench/dut/wallypipelinedsoc/uncore/uart/uart/RXRDYb
-add wave -noupdate -group UART /testbench/dut/wallypipelinedsoc/uncore/uart/uart/HCLK
-add wave -noupdate -group UART /testbench/dut/wallypipelinedsoc/uncore/uart/uart/HSELUART
-add wave -noupdate -group UART /testbench/dut/wallypipelinedsoc/uncore/uart/uart/HADDR
-add wave -noupdate -group UART /testbench/dut/wallypipelinedsoc/uncore/uart/uart/HWRITE
-add wave -noupdate -group UART /testbench/dut/wallypipelinedsoc/uncore/uart/uart/HWDATA
-add wave -noupdate -group SDC -color Gold -label {AHBLite FSM} /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/CurrState
-add wave -noupdate -group SDC /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/HCLK
-add wave -noupdate -group SDC /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/CLKGate
-add wave -noupdate -group SDC /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/SDCCLKIn
-add wave -noupdate -group SDC /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/SDCCLK
-add wave -noupdate -group SDC -expand -group {SDC interfce} /testbench/dut/wallypipelinedsoc/SDCCLK
-add wave -noupdate -group SDC -expand -group {SDC interfce} -color Brown /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/sd_top/my_sd_cmd_fsm/o_SD_CMD_OE
-add wave -noupdate -group SDC -expand -group {SDC interfce} /testbench/dut/SDCCmdOut
-add wave -noupdate -group SDC -expand -group {SDC interfce} /testbench/dut/SDCCmdIn
-add wave -noupdate -group SDC -expand -group {SDC interfce} /testbench/dut/SDCDatIn
-add wave -noupdate -group SDC -expand -group {SDC FSMs} -color Gold -label {cmd fsm} /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/sd_top/my_sd_cmd_fsm/r_curr_state
-add wave -noupdate -group SDC -expand -group {SDC FSMs} -color Gold -label {dat fsm} /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/sd_top/my_sd_dat_fsm/r_curr_state
-add wave -noupdate -group SDC -expand -group {SDC FSMs} -color Gold -label {clk fsm} /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/sd_top/my_clk_fsm/r_curr_state
-add wave -noupdate -group SDC -expand -group registers /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/CLKDiv
-add wave -noupdate -group SDC -expand -group registers /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/Command
-add wave -noupdate -group SDC -expand -group registers -color {Medium Orchid} /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/Status
-add wave -noupdate -group SDC -expand -group registers /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/Address
-add wave -noupdate -group SDC -group {AHBLite interface} -color Aquamarine /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/HSELSDC
-add wave -noupdate -group SDC -group {AHBLite interface} /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/HADDR
-add wave -noupdate -group SDC -group {AHBLite interface} /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/HADDRDelay
-add wave -noupdate -group SDC -group {AHBLite interface} /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/HWRITE
-add wave -noupdate -group SDC -group {AHBLite interface} /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/HREADY
-add wave -noupdate -group SDC -group {AHBLite interface} /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/HTRANS
-add wave -noupdate -group SDC -group {AHBLite interface} /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/HWDATA
-add wave -noupdate -group SDC -group {AHBLite interface} /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/HREADSDC
-add wave -noupdate -group SDC -group {AHBLite interface} /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/HRESPSDC
-add wave -noupdate -group SDC -group {AHBLite interface} -color Goldenrod /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/HREADYSDC
-add wave -noupdate -group SDC /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/InitTrans
-add wave -noupdate -group SDC /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/sd_top/o_ERROR_CODE_Q
-add wave -noupdate -group SDC /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/sd_top/o_DATA_VALID
-add wave -noupdate -group SDC /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/sd_top/ReadData
-add wave -noupdate -group SDC /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/WordCount
-add wave -noupdate -group SDC /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/HREADSDC
-add wave -noupdate -group SDC /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/sd_top/o_READY_FOR_READ
-add wave -noupdate -group SDC -group {Instruction Counter control} /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/sd_top/w_IC_EN
-add wave -noupdate -group SDC -group {Instruction Counter control} /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/sd_top/w_IC_RST
-add wave -noupdate -group SDC -group {Instruction Counter control} /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/sd_top/w_IC_UP_DOWN
-add wave -noupdate -group SDC -group {Instruction Counter control} /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/sd_top/r_IC_OUT
-add wave -noupdate -group boottim /testbench/dut/wallypipelinedsoc/uncore/bootram/bootram/HADDR
-add wave -noupdate -group boottim /testbench/dut/wallypipelinedsoc/uncore/bootram/bootram/A
-add wave -noupdate -group boottim /testbench/dut/wallypipelinedsoc/uncore/bootram/bootram/HWADDR
-add wave -noupdate -group boottim /testbench/dut/wallypipelinedsoc/uncore/bootram/bootram/HSELTim
-add wave -noupdate -group boottim /testbench/dut/wallypipelinedsoc/uncore/bootram/bootram/HREADYTim
-add wave -noupdate -group boottim /testbench/dut/wallypipelinedsoc/uncore/bootram/bootram/HRESPTim
-add wave -noupdate -group boottim /testbench/dut/wallypipelinedsoc/uncore/bootram/bootram/initTrans
-add wave -noupdate /testbench/dut/wallypipelinedsoc/uncore/HSELRegions
-add wave -noupdate /testbench/dut/wallypipelinedsoc/uncore/HSELDDR4
-add wave -noupdate /testbench/ram/HSELTim
-add wave -noupdate /testbench/dut/wallypipelinedsoc/uncore/HRDATAEXT
-add wave -noupdate /testbench/dut/wallypipelinedsoc/uncore/HREADYEXT
-add wave -noupdate /testbench/dut/wallypipelinedsoc/uncore/HRESPEXT
-add wave -noupdate /testbench/dut/wallypipelinedsoc/uncore/HSELEXT
-add wave -noupdate /testbench/ram/HCLK
-add wave -noupdate /testbench/ram/HRESETn
-add wave -noupdate /testbench/ram/HSELTim
-add wave -noupdate /testbench/ram/HADDR
-add wave -noupdate /testbench/ram/HWRITE
-add wave -noupdate /testbench/ram/HREADY
-add wave -noupdate /testbench/ram/HTRANS
-add wave -noupdate /testbench/ram/HWDATA
-add wave -noupdate /testbench/ram/HREADTim
-add wave -noupdate /testbench/ram/HRESPTim
-add wave -noupdate /testbench/ram/HREADYTim
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNext1F
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/BPPredWrongE
+add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PrivilegedChangePCM
+add wave -noupdate -group RegFile -expand /testbench/dut/core/ieu/dp/regf/rf
+add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a1
+add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a2
+add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a3
+add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/rd1
+add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/rd2
+add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/we3
+add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/wd3
+add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ReadDataW
+add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/CSRReadValW
+add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultSrcW
+add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultW
+add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/A
+add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/B
+add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/ALUControl
+add wave -noupdate -group alu -divider internals
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs1D
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs2D
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs1E
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs2E
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdE
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdM
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdW
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/MemReadE
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RegWriteM
+add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RegWriteW
+add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/ForwardAE
+add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/ForwardBE
+add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/LoadStallD
+add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/WriteDataE
+add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/ALUResultE
+add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcAE
+add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcBE
+add wave -noupdate -group AHB -color Gold /testbench/dut/core/ebu/BusState
+add wave -noupdate -group AHB /testbench/dut/core/ebu/NextBusState
+add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/core/ebu/AtomicMaskedM
+add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/core/ebu/LSUBusSize
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HCLK
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HRESETn
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HRDATA
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HREADY
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HRESP
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HADDR
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HWDATA
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HWRITE
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HSIZE
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HBURST
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HPROT
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HTRANS
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HMASTLOCK
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HADDRD
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HSIZED
+add wave -noupdate -group AHB /testbench/dut/core/ebu/HWRITED
+add wave -noupdate -group lsu -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/interlockfsm/InterlockCurrState
+add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW
+add wave -noupdate -group lsu /testbench/dut/core/lsu/InterlockStall
+add wave -noupdate -group lsu /testbench/dut/core/lsu/LSUStallM
+add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM
+add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM
+add wave -noupdate -group lsu /testbench/dut/core/lsu/WriteDataM
+add wave -noupdate -group lsu /testbench/dut/core/lsu/bus/busdp/SelUncachedAdr
+add wave -noupdate -group lsu -group bus -color Gold /testbench/dut/core/lsu/bus/busdp/busfsm/BusCurrState
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/BusStall
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusRead
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusWrite
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusAdr
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusAck
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusHRDATA
+add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUBusHWDATA
+add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/RAdr
+add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/RAdrD}
+add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay}
+add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
+add wave -noupdate -group lsu -expand -group dcache -expand -group flush -radix unsigned /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr
+add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
+add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirtyWay
+add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/VictimTag
+add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/CacheableM
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusWriteData
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/RAdr
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Valid}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Valid}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Valid}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Valid}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
+add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimTag
+add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay
+add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirtyWay
+add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimDirty
+add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/RW
+add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr
+add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr
+add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/Atomic
+add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache
+add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
+add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM
+add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/FinalWriteDataM
+add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
+add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheFetchLine
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteLine
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusWriteData
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress
+add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault
+add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM
+add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM
+add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr
+add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
+add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal
+add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/AtomicAllowed
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM
+add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM
+add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress
+add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM
+add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM
+add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW
+add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW
+add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
+add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
+add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
+add wave -noupdate -group lsu -group ptwalker -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/WalkerState
+add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PCF
+add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWReadPTE
+add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWAdr
+add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PTE
+add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/ITLBWriteF
+add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DTLBWriteM
+add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HCLK
+add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HSELPLIC
+add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HADDR
+add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HWRITE
+add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HREADY
+add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HTRANS
+add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HWDATA
+add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/UARTIntr
+add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/GPIOIntr
+add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HREADPLIC
+add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HRESPPLIC
+add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HREADYPLIC
+add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intClaim
+add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intEn
+add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intInProgress
+add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intPending
+add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intPriority
+add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intThreshold
+add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/nextIntPending
+add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/requests
+add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/threshMask
+add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HCLK
+add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HSELGPIO
+add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HADDR
+add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HWDATA
+add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HWRITE
+add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HREADY
+add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HTRANS
+add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HREADGPIO
+add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HRESPGPIO
+add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HREADYGPIO
+add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOPinsIn
+add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOPinsOut
+add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOPinsEn
+add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOIntr
+add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HCLK
+add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HSELCLINT
+add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HADDR
+add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HWRITE
+add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HWDATA
+add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HREADY
+add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HTRANS
+add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HREADCLINT
+add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HRESPCLINT
+add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HREADYCLINT
+add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/MTIME
+add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/MTIMECMP
+add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/TimerIntM
+add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/SwIntM
+add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HCLK
+add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HRESETn
+add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HSELUART
+add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HADDR
+add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HWRITE
+add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HWDATA
+add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HREADUART
+add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HRESPUART
+add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HREADYUART
+add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/LSR
+add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/MCR
+add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/MSR
+add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/RBR
+add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/TXHR
+add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/LCR
+add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/INTR
+add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxstate
+add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/txstate
+add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/txbitssent
+add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/txbitsexpected
+add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxbitsreceived
+add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxbitsexpected
+add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxdata
+add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxshiftreg
+add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/SOUTbit
+add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/SINsync
+add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/txsr
+add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/SIN
+add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/SOUT
+add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/RTSb
+add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/DTRb
+add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/OUT1b
+add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/OUT2b
+add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/DSRb
+add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/DCDb
+add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/CTSb
+add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/TXRDYb
+add wave -noupdate -group uart -expand -group {Off-Chip Interface} /testbench/dut/uncore/uart/uart/RXRDYb
+add wave -noupdate -group {debug trace} -expand -group mem -color Yellow /testbench/dut/core/FlushW
+add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/core/PCM
+add wave -noupdate -group {debug trace} -expand -group mem -color Brown /testbench/dut/core/hzu/TrapM
+add wave -noupdate -group {debug trace} -expand -group wb /testbench/PCW
+add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PCNext2F
+add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PrivilegedNextPCM
+add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PrivilegedChangePCM
+add wave -noupdate -group ifu -color Gold /testbench/dut/core/lsu/bus/busdp/busfsm/BusCurrState
+add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUBusRead
+add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUBusAdr
+add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUBusAck
+add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUBusHRDATA
+add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillF
+add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/CurrState
+add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillDataLine0
+add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SelSpillF
+add wave -noupdate -group ifu -expand -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState
+add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/ITLBMissF
+add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SelAdr
+add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCNextF
+add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCPF
+add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay
+add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF
+add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/FinalInstrRawF
+add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr
+add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck
+add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusWriteData
+add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite
+add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/ITLBMissF
+add wave -noupdate -group ifu -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress
+add wave -noupdate -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]}
+add wave -noupdate -group {Performance Counters} -label MINSTRET -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]}
+add wave -noupdate -group {Performance Counters} -label {LOAD STORE HAZARD} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]}
+add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BP DIRECTION WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]}
+add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BP INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]}
+add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BTA/JTA WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]}
+add wave -noupdate -group {Performance Counters} -expand -group BRP -label {JAL(R) INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]}
+add wave -noupdate -group {Performance Counters} -expand -group BRP -label {RAS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]}
+add wave -noupdate -group {Performance Counters} -expand -group BRP -label {RETURN INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]}
+add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]}
+add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {ICACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]}
+add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {ICACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]}
+add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]}
+add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]}
+add wave -noupdate /testbench/dut/SDCCmdIn
+add wave -noupdate /testbench/dut/SDCCmdOut
+add wave -noupdate /testbench/dut/SDCCmdOE
+add wave -noupdate /testbench/dut/SDCDatIn
+add wave -noupdate /testbench/dut/SDCCLK
+add wave -noupdate -color Gold -label {cmd fsm} /testbench/dut/uncore/sdc/SDC/sd_top/my_sd_cmd_fsm/r_curr_state
+add wave -noupdate -color Gold -label {dat fsm} /testbench/dut/uncore/sdc/SDC/sd_top/my_sd_dat_fsm/r_curr_state
+add wave -noupdate -color Gold -label {clk fsm} /testbench/dut/uncore/sdc/SDC/sd_top/my_clk_fsm/r_curr_state
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 6} {1090427 ns} 1} {{Cursor 3} {1157417 ns} 1} {{Cursor 4} {2324620 ns} 0}
-quietly wave cursor active 3
+WaveRestoreCursors {{Cursor 5} {2125334 ns} 0}
+quietly wave cursor active 1
 configure wave -namecolwidth 250
-configure wave -valuecolwidth 297
+configure wave -valuecolwidth 177
 configure wave -justifyvalue left
 configure wave -signalnamewidth 1
 configure wave -snapdistance 10
@@ -586,4 +525,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {2324497 ns} {2324741 ns}
+WaveRestoreZoom {2124499 ns} {2128105 ns}
diff --git a/pipelined/regression/regression-wally b/pipelined/regression/regression-wally
index a5535b49..cbd2caf7 100755
--- a/pipelined/regression/regression-wally
+++ b/pipelined/regression/regression-wally
@@ -62,7 +62,7 @@ tc = TestCase(
       grepstr="400100000 instructions")
 configs.append(tc)
 
-tests64gc = ["arch64i", "arch64priv", "arch64c",  "arch64m", "arch64d", "imperas64i", "imperas64f", "imperas64d", "imperas64m", "wally64a",  "imperas64c", "wally64priv", "wally64periph"] # , "imperas64mmu" "wally64i", #,  "testsBP64"] 
+tests64gc = ["arch64i", "arch64priv", "arch64c",  "arch64m", "arch64d", "imperas64i", "imperas64f", "imperas64d", "imperas64m", "wally64a",  "imperas64c", "wally64periph"] # , "imperas64mmu" "wally64i", #,  "testsBP64"] 
 for test in tests64gc:
   tc = TestCase(
         name=test,
diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv
index 489ee953..2628726d 100644
--- a/pipelined/src/privileged/csr.sv
+++ b/pipelined/src/privileged/csr.sv
@@ -33,9 +33,8 @@
 `include "wally-config.vh"
 
 module csr #(parameter
-  // Constants
-  UIP_REGW = 12'b0, // N user-mode exceptions not supported
-  UIE_REGW = 12'b0
+    MIP = 12'h344,
+    SIP = 12'h144
   ) (
   input  logic             clk, reset,
   input  logic             FlushE, FlushM, FlushW,
@@ -76,8 +75,11 @@ module csr #(parameter
 );
 
   localparam NOP = 32'h13;
-  logic [`XLEN-1:0] CSRMReadValM, CSRSReadValM, CSRUReadValM, CSRCReadValM, CSRReadValM;
-  logic [`XLEN-1:0] CSRSrcM, CSRRWM, CSRRSM, CSRRCM, CSRWriteValM;
+  logic [`XLEN-1:0] CSRMReadValM, CSRSReadValM, CSRUReadValM, CSRCReadValM;
+(* mark_debug = "true" *)  logic [`XLEN-1:0] CSRReadValM;  
+(* mark_debug = "true" *)  logic [`XLEN-1:0] CSRSrcM;
+  logic [`XLEN-1:0] CSRRWM, CSRRSM, CSRRCM;  
+(* mark_debug = "true" *)  logic [`XLEN-1:0] CSRWriteValM;
  
 (* mark_debug = "true" *)  logic [`XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW;
   logic [31:0]     MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW;
@@ -92,6 +94,8 @@ module csr #(parameter
   //logic [11:0] UIP_REGW, UIE_REGW = 0; // N user-mode exceptions not supported
   logic        IllegalCSRCAccessM, IllegalCSRMAccessM, IllegalCSRSAccessM, IllegalCSRUAccessM, InsufficientCSRPrivilegeM;
   logic IllegalCSRMWriteReadonlyM;
+  logic [`XLEN-1:0] CSRReadVal2M;
+  logic [11:0] IP_REGW_writeable;
   
   logic InstrValidNotFlushedM;
   assign InstrValidNotFlushedM = ~StallW & ~FlushW;
@@ -100,10 +104,15 @@ module csr #(parameter
   always_comb begin
     // Choose either rs1 or uimm[4:0] as source
     CSRSrcM = InstrM[14] ? {{(`XLEN-5){1'b0}}, InstrM[19:15]} : SrcAM;
+
+    // CSR set and clear for MIP/SIP should only touch internal state, not interrupt inputs
+    if (CSRAdrM == MIP | CSRAdrM == SIP) CSRReadVal2M = {{(`XLEN-12){1'b0}}, IP_REGW_writeable};
+    else                                 CSRReadVal2M = CSRReadValM;
+
     // Compute AND/OR modification
     CSRRWM = CSRSrcM;
-    CSRRSM = CSRReadValM | CSRSrcM;
-    CSRRCM = CSRReadValM & ~CSRSrcM;
+    CSRRSM = CSRReadVal2M | CSRSrcM;
+    CSRRCM = CSRReadVal2M & ~CSRSrcM;
     case (InstrM[13:12])
       2'b01:  CSRWriteValM = CSRRWM;
       2'b10:  CSRWriteValM = CSRRSM;
@@ -125,7 +134,7 @@ module csr #(parameter
   csri   csri(.clk, .reset, .InstrValidNotFlushedM, .StallW, 
               .CSRMWriteM, .CSRSWriteM, .CSRWriteValM, .CSRAdrM, 
               .MExtIntM, .SExtIntM, .TimerIntM, .SwIntM,
-              .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .MIDELEG_REGW);
+              .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .MIDELEG_REGW, .IP_REGW_writeable);
   csrsr csrsr(.clk, .reset, .StallW,
               .WriteMSTATUSM, .WriteSSTATUSM, 
               .TrapM, .FRegWriteM, .NextPrivilegeModeM, .PrivilegeModeW,
diff --git a/pipelined/src/privileged/csri.sv b/pipelined/src/privileged/csri.sv
index 68a265b5..343a900d 100644
--- a/pipelined/src/privileged/csri.sv
+++ b/pipelined/src/privileged/csri.sv
@@ -37,17 +37,17 @@ module csri #(parameter
     SIE = 12'h104,
     SIP = 12'h144
   ) (
-    input  logic             clk, reset, 
-    input  logic             InstrValidNotFlushedM, StallW,
-    input  logic             CSRMWriteM, CSRSWriteM,
-    input  logic [`XLEN-1:0] CSRWriteValM,
-    input  logic [11:0]      CSRAdrM,
-    input  logic             MExtIntM, SExtIntM, TimerIntM, SwIntM,
-    input  logic [11:0]      MIDELEG_REGW,
-    output logic [11:0]      MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW
+    input logic 			clk, reset, 
+    input logic 			InstrValidNotFlushedM, StallW,
+    input logic 			CSRMWriteM, CSRSWriteM,
+    input logic [`XLEN-1:0] CSRWriteValM,
+    input logic [11:0] 		CSRAdrM,
+    (* mark_debug = "true" *)    input logic MExtIntM, SExtIntM, TimerIntM, SwIntM,
+    input logic [11:0] 		MIDELEG_REGW,
+    output logic [11:0] 	MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW, 
+    (* mark_debug = "true" *) output logic [11:0]   IP_REGW_writeable // only SEIP, STIP, SSIP are actually writeable; the rest are hardwired to 0
   );
 
-  logic [11:0]     IP_REGW_writeable; // only SEIP, STIP, SSIP are actually writeable; the rest are hardwired to 0
   logic [11:0]     IP_REGW, IE_REGW;
   logic [11:0]     MIP_WRITE_MASK, SIP_WRITE_MASK, MIE_WRITE_MASK;
   logic            WriteMIPM, WriteMIEM, WriteSIPM, WriteSIEM;
diff --git a/pipelined/src/privileged/csrm.sv b/pipelined/src/privileged/csrm.sv
index 8315d38f..86171100 100644
--- a/pipelined/src/privileged/csrm.sv
+++ b/pipelined/src/privileged/csrm.sv
@@ -78,8 +78,8 @@ module csrm #(parameter
     output logic [`XLEN-1:0] CSRMReadValM, MTVEC_REGW,
     (* mark_debug = "true" *)  output logic [`XLEN-1:0] MEPC_REGW,    
     output logic [31:0]      MCOUNTEREN_REGW, MCOUNTINHIBIT_REGW, 
-    output logic [`XLEN-1:0] MEDELEG_REGW,
-    output logic [11:0]      MIDELEG_REGW,
+(* mark_debug = "true" *)      output logic [`XLEN-1:0] MEDELEG_REGW,
+(* mark_debug = "true" *)      output logic [11:0]      MIDELEG_REGW,
     // 64-bit registers in RV64, or two 32-bit registers in RV32
     //output var logic [63:0]      PMPCFG_ARRAY_REGW[`PMP_ENTRIES/8-1:0],
     output 		     var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
diff --git a/pipelined/src/uncore/clint.sv b/pipelined/src/uncore/clint.sv
index f3ee4f5c..c2d9f0f5 100644
--- a/pipelined/src/uncore/clint.sv
+++ b/pipelined/src/uncore/clint.sv
@@ -32,25 +32,25 @@
 `include "wally-config.vh"
 
 module clint (
-  input  logic             HCLK, HRESETn, TIMECLK,
-  input  logic             HSELCLINT,
-  input  logic [15:0]      HADDR,
-  input  logic [3:0]       HSIZED,
-  input  logic             HWRITE,
-  input  logic [`XLEN-1:0] HWDATA,
-  input  logic             HREADY,
-  input  logic [1:0]       HTRANS,
+  input logic 			   HCLK, HRESETn, TIMECLK,
+  input logic 			   HSELCLINT,
+  input logic [15:0] 	   HADDR,
+  input logic [3:0] 	   HSIZED,
+  input logic 			   HWRITE,
+  input logic [`XLEN-1:0]  HWDATA,
+  input logic 			   HREADY,
+  input logic [1:0] 	   HTRANS,
   output logic [`XLEN-1:0] HREADCLINT,
-  output logic             HRESPCLINT, HREADYCLINT,
-  output logic [63:0]      MTIME, 
-  output logic             TimerIntM, SwIntM);
+  output logic 			   HRESPCLINT, HREADYCLINT,
+  (* mark_debug = "true" *) output logic [63:0] MTIME, 
+  output logic 			   TimerIntM, SwIntM);
 
   logic        MSIP;
 
   logic [15:0] entry, entryd;
   logic memwrite;
   logic initTrans;
-  logic [63:0] MTIMECMP;
+  (* mark_debug = "true" *)    logic [63:0] MTIMECMP;
   logic [`XLEN/8-1:0] ByteMaskM;
   integer             i;
 
diff --git a/pipelined/src/uncore/plic.sv b/pipelined/src/uncore/plic.sv
index 6e9f95b8..fd3f5d1d 100644
--- a/pipelined/src/uncore/plic.sv
+++ b/pipelined/src/uncore/plic.sv
@@ -70,9 +70,9 @@ module plic (
   
   // context-dependent signals
   logic [`C-1:0][2:0]       intThreshold;
-  logic [`C-1:0][`N:1]      intEn;
+    (* mark_debug = "true" *)  logic [`C-1:0][`N:1]      intEn;
   logic [`C-1:0][5:0]       intClaim; // ID's are 6 bits if we stay within 63 sources
-  logic [`C-1:0][7:1][`N:1] irqMatrix;
+    (* mark_debug = "true" *)  logic [`C-1:0][7:1][`N:1] irqMatrix;
   logic [`C-1:0][7:1]       priorities_with_irqs;
   logic [`C-1:0][7:1]       max_priority_with_irqs;
   logic [`C-1:0][`N:1]      irqs_at_max_priority;
diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv
index 43b61e6d..1e835504 100644
--- a/pipelined/src/wally/wallypipelinedcore.sv
+++ b/pipelined/src/wally/wallypipelinedcore.sv
@@ -66,7 +66,7 @@ module wallypipelinedcore (
   logic [1:0]             AtomicE;
   logic [1:0]             AtomicM;
   logic [`XLEN-1:0]     ForwardedSrcAE, ForwardedSrcBE; //, SrcAE, SrcBE;
-  logic [`XLEN-1:0]         SrcAM;
+(* mark_debug = "true" *)  logic [`XLEN-1:0]         SrcAM;
   logic [2:0]             Funct3E;
   //  logic [31:0] InstrF;
   logic [31:0]             InstrD, InstrW;
diff --git a/pipelined/testbench/testbench-fpga.sv b/pipelined/testbench/testbench-fpga.sv
index 230d9389..5997180f 100644
--- a/pipelined/testbench/testbench-fpga.sv
+++ b/pipelined/testbench/testbench-fpga.sv
@@ -1,11 +1,11 @@
 ///////////////////////////////////////////
-// testbench-imperas.sv
+// testbench.sv
 //
 // Written: David_Harris@hmc.edu 9 January 2021
 // Modified: 
 //
 // Purpose: Wally Testbench and helper modules
-//          Applies test programs from the Imperas suite
+//          Applies test programs from the riscv-arch-test and Imperas suites
 // 
 // A component of the Wally configurable RISC-V project.
 // 
@@ -30,487 +30,30 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"
+`include "tests.vh"
 
-module testbench();
-  parameter DEBUG = 0;
-  parameter TESTSPERIPH = 0; // set to 0 for regression
-  parameter TESTSPRIV = 0; // set to 0 for regression
-  
+module testbench;
+  parameter DEBUG=0;
+  parameter TEST="none";
+ 
   logic        clk;
-  logic        reset;
+  logic        reset_ext, reset;
 
   parameter SIGNATURESIZE = 5000000;
 
   int test, i, errors, totalerrors;
   logic [31:0] sig32[0:SIGNATURESIZE];
   logic [`XLEN-1:0] signature[0:SIGNATURESIZE];
-  logic [`XLEN-1:0] testadr;
+  logic [`XLEN-1:0] testadr, testadrNoBase;
   string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
   logic [31:0] InstrW;
-  logic [`XLEN-1:0] meminit;
 
-  string tests32mmu[] = '{
-    "rv32mmu/WALLY-MMU-SV32", "3000"
-    //"rv32mmu/WALLY-PMA", "3000",
-    //"rv32mmu/WALLY-PMA", "3000"
-    };
+string tests[];
+logic [3:0] dummy;
 
-  string tests64mmu[] = '{
-    "rv64mmu/WALLY-MMU-SV48", "3000",
-    "rv64mmu/WALLY-MMU-SV39", "3000"
-    //"rv64mmu/WALLY-PMA", "3000",
-    //"rv64mmu/WALLY-PMA", "3000"
-  };
-
-  
-string tests32f[] = '{
-    "rv32f/I-FADD-S-01", "2000",
-    "rv32f/I-FCLASS-S-01", "2000",
-    "rv32f/I-FCVT-S-W-01", "2000",
-    "rv32f/I-FCVT-S-WU-01", "2000",
-    "rv32f/I-FCVT-W-S-01", "2000",
-    "rv32f/I-FCVT-WU-S-01", "2000",
-    "rv32f/I-FDIV-S-01", "2000",
-    "rv32f/I-FEQ-S-01", "2000",
-    "rv32f/I-FLE-S-01", "2000",
-    "rv32f/I-FLT-S-01", "2000",
-    "rv32f/I-FMADD-S-01", "2000",
-    "rv32f/I-FMAX-S-01", "2000",
-    "rv32f/I-FMIN-S-01", "2000",
-    "rv32f/I-FMSUB-S-01", "2000",
-    "rv32f/I-FMUL-S-01", "2000",
-    "rv32f/I-FMV-W-X-01", "2000",
-    "rv32f/I-FMV-X-W-01", "2000",
-    "rv32f/I-FNMADD-S-01", "2000",
-    "rv32f/I-FNMSUB-S-01", "2000",
-    "rv32f/I-FSGNJ-S-01", "2000",
-    "rv32f/I-FSGNJN-S-01", "2000",
-    "rv32f/I-FSGNJX-S-01", "2000",
-    "rv32f/I-FSQRT-S-01", "2000",
-    "rv32f/I-FSW-01", "2000",
-    "rv32f/I-FLW-01", "2110",
-    "rv32f/I-FSUB-S-01", "2000"
-  };
-
-  string tests64f[] = '{
-    "rv64f/I-FLW-01", "2110",
-    "rv64f/I-FMV-W-X-01", "2000",
-    "rv64f/I-FMV-X-W-01", "2000",
-    "rv64f/I-FSW-01", "2000",
-    "rv64f/I-FCLASS-S-01", "2000",
-    "rv64f/I-FADD-S-01", "2000",
-//    "rv64f/I-FCVT-S-L-01", "2000",
-//    "rv64f/I-FCVT-S-LU-01", "2000",
-//    "rv64f/I-FCVT-S-W-01", "2000",
-//    "rv64f/I-FCVT-S-WU-01", "2000",
-    "rv64f/I-FCVT-L-S-01", "2000",
-    "rv64f/I-FCVT-LU-S-01", "2000",
-    "rv64f/I-FCVT-W-S-01", "2000",
-    "rv64f/I-FCVT-WU-S-01", "2000",
-    "rv64f/I-FDIV-S-01", "2000",
-    "rv64f/I-FEQ-S-01", "2000",
-    "rv64f/I-FLE-S-01", "2000",
-    "rv64f/I-FLT-S-01", "2000",
-    "rv64f/I-FMADD-S-01", "2000",
-    "rv64f/I-FMAX-S-01", "2000",
-    "rv64f/I-FMIN-S-01", "2000",
-    "rv64f/I-FMSUB-S-01", "2000",
-    "rv64f/I-FMUL-S-01", "2000",
-    "rv64f/I-FNMADD-S-01", "2000",
-    "rv64f/I-FNMSUB-S-01", "2000",
-    "rv64f/I-FSGNJ-S-01", "2000",
-    "rv64f/I-FSGNJN-S-01", "2000",
-    "rv64f/I-FSGNJX-S-01", "2000",
-    "rv64f/I-FSQRT-S-01", "2000",
-    "rv64f/I-FSUB-S-01", "2000"
-  };
-
-  string tests64d[] = '{
-    "rv64d/I-FSD-01", "2000",
-    "rv64d/I-FLD-01", "2420",
-    "rv64d/I-FMV-X-D-01", "2000",
-    "rv64d/I-FMV-D-X-01", "2000",
-    "rv64d/I-FDIV-D-01", "2000",
-    "rv64d/I-FNMADD-D-01", "2000",
-    "rv64d/I-FNMSUB-D-01", "2000",
-    "rv64d/I-FMSUB-D-01", "2000",
-    "rv64d/I-FMAX-D-01", "2000",
-    "rv64d/I-FMIN-D-01", "2000",
-    "rv64d/I-FLE-D-01", "2000",
-    "rv64d/I-FLT-D-01", "2000",
-    "rv64d/I-FEQ-D-01", "2000",
-    "rv64d/I-FADD-D-01", "2000",
-    "rv64d/I-FCLASS-D-01", "2000",
-    "rv64d/I-FMADD-D-01", "2000",
-    "rv64d/I-FMUL-D-01", "2000",
-    "rv64d/I-FSGNJ-D-01", "2000",
-    "rv64d/I-FSGNJN-D-01", "2000",
-    "rv64d/I-FSGNJX-D-01", "2000",
-    "rv64d/I-FSQRT-D-01", "2000",
-    "rv64d/I-FSUB-D-01", "2000",
-//    "rv64d/I-FCVT-D-L-01", "2000",
-//    "rv64d/I-FCVT-D-LU-01", "2000",
-    "rv64d/I-FCVT-D-S-01", "2000", 
-//    "rv64d/I-FCVT-D-W-01", "2000",
-//    "rv64d/I-FCVT-D-WU-01", "2000",
-    "rv64d/I-FCVT-L-D-01", "2000",
-    "rv64d/I-FCVT-LU-D-01", "2000",
-    "rv64d/I-FCVT-S-D-01", "2000", 
-    "rv64d/I-FCVT-W-D-01", "2000",
-    "rv64d/I-FCVT-WU-D-01", "2000"
-};
-
-  string tests64a[] = '{
-    "rv64a/WALLY-AMO", "2110",
-    "rv64a/WALLY-LRSC", "2110"
-  };
-
-  string tests64m[] = '{
-    "rv64m/I-MUL-01", "3000",
-    "rv64m/I-MULH-01", "3000",
-    "rv64m/I-MULHSU-01", "3000",
-    "rv64m/I-MULHU-01", "3000",
-    "rv64m/I-MULW-01", "3000",
-    "rv64m/I-DIV-01", "3000",
-    "rv64m/I-DIVU-01", "3000",
-    "rv64m/I-DIVUW-01", "3000",
-    "rv64m/I-DIVW-01", "3000",
-    "rv64m/I-REM-01", "3000",
-    "rv64m/I-REMU-01", "3000",
-    "rv64m/I-REMUW-01", "3000",
-    "rv64m/I-REMW-01", "3000"
-  };
-
-  string tests64ic[] = '{
-    "rv64ic/I-C-ADD-01", "3000",
-    "rv64ic/I-C-ADDI-01", "3000",
-    "rv64ic/I-C-ADDIW-01", "3000",
-    "rv64ic/I-C-ADDW-01", "3000",
-    "rv64ic/I-C-AND-01", "3000",
-    "rv64ic/I-C-ANDI-01", "3000",
-    "rv64ic/I-C-BEQZ-01", "3000",
-    "rv64ic/I-C-BNEZ-01", "3000",
-    "rv64ic/I-C-EBREAK-01", "2000",
-    "rv64ic/I-C-J-01", "3000",
-    "rv64ic/I-C-JALR-01", "4000",
-    "rv64ic/I-C-JR-01", "4000",
-    "rv64ic/I-C-LD-01", "3420",
-    "rv64ic/I-C-LDSP-01", "3420",
-    "rv64ic/I-C-LI-01", "3000",
-    "rv64ic/I-C-LUI-01", "2000",
-    "rv64ic/I-C-LW-01", "3110",
-    "rv64ic/I-C-LWSP-01", "3110",
-    "rv64ic/I-C-MV-01", "3000",
-    "rv64ic/I-C-NOP-01", "2000",
-    "rv64ic/I-C-OR-01", "3000",
-    "rv64ic/I-C-SD-01", "3000",
-    "rv64ic/I-C-SDSP-01", "3000",
-    "rv64ic/I-C-SLLI-01", "3000",
-    "rv64ic/I-C-SRAI-01", "3000",
-    "rv64ic/I-C-SRLI-01", "3000",
-    "rv64ic/I-C-SUB-01", "3000",
-    "rv64ic/I-C-SUBW-01", "3000",
-    "rv64ic/I-C-SW-01", "3000",
-    "rv64ic/I-C-SWSP-01", "3000",
-    "rv64ic/I-C-XOR-01", "3000"
-  };
-
-  string tests64iNOc[] = {
-    "rv64i/I-MISALIGN_JMP-01","2000"
-  };
-
-  string tests64i[] = '{
-    //"rv64i/WALLY-PIPELINE-100K", "f7ff0",
-    "rv64i/I-ADD-01", "3000",
-    "rv64i/I-ADDI-01", "3000",
-    "rv64i/I-ADDIW-01", "3000",
-    "rv64i/I-ADDW-01", "3000",
-    "rv64i/I-AND-01", "3000",
-    "rv64i/I-ANDI-01", "3000",
-    "rv64i/I-AUIPC-01", "3000",
-    "rv64i/I-BEQ-01", "4000",
-    "rv64i/I-BGE-01", "4000",
-    "rv64i/I-BGEU-01", "4000",
-    "rv64i/I-BLT-01", "4000",
-    "rv64i/I-BLTU-01", "4000",
-    "rv64i/I-BNE-01", "4000",
-    "rv64i/I-DELAY_SLOTS-01", "2000",
-    "rv64i/I-EBREAK-01", "2000",
-    "rv64i/I-ECALL-01", "2000",
-    "rv64i/I-ENDIANESS-01", "2010",
-    "rv64i/I-IO-01", "2050",
-    "rv64i/I-JAL-01", "3000",
-    "rv64i/I-JALR-01", "4000",
-    "rv64i/I-LB-01", "4020",
-    "rv64i/I-LBU-01", "4020",
-    "rv64i/I-LD-01", "4420",
-    "rv64i/I-LH-01", "4050",
-    "rv64i/I-LHU-01", "4050",
-    "rv64i/I-LUI-01", "2000",
-    "rv64i/I-LW-01", "4110",
-    "rv64i/I-LWU-01", "4110", 
-    "rv64i/I-MISALIGN_LDST-01", "2010",
-    "rv64i/I-NOP-01", "2000",
-    "rv64i/I-OR-01", "3000",
-    "rv64i/I-ORI-01", "3000",
-    "rv64i/I-RF_size-01", "2000",
-    "rv64i/I-RF_width-01", "2000",
-    "rv64i/I-RF_x0-01", "2010",
-    "rv64i/I-SB-01", "4000",
-    "rv64i/I-SD-01", "4000",
-    "rv64i/I-SH-01", "4000",
-    "rv64i/I-SLL-01", "3000",
-    "rv64i/I-SLLI-01", "3000",
-    "rv64i/I-SLLIW-01", "3000",
-    "rv64i/I-SLLW-01", "3000",
-    "rv64i/I-SLT-01", "3000",
-    "rv64i/I-SLTI-01", "3000",
-    "rv64i/I-SLTIU-01", "3000",
-    "rv64i/I-SLTU-01", "3000",
-    "rv64i/I-SRA-01", "3000",
-    "rv64i/I-SRAI-01", "3000",
-    "rv64i/I-SRAIW-01", "3000",
-    "rv64i/I-SRAW-01", "3000",
-    "rv64i/I-SRL-01", "3000",
-    "rv64i/I-SRLI-01", "3000",
-    "rv64i/I-SRLIW-01", "3000",
-    "rv64i/I-SRLW-01", "3000",
-    "rv64i/I-SUB-01", "3000",
-    "rv64i/I-SUBW-01", "3000",
-    "rv64i/I-SW-01", "4000",
-    "rv64i/I-XOR-01", "3000",
-    "rv64i/I-XORI-01", "3000",
-    "rv64i/WALLY-ADD", "4000",
-    "rv64i/WALLY-SUB", "4000",
-    "rv64i/WALLY-ADDI", "3000",
-    "rv64i/WALLY-ANDI", "3000",
-    "rv64i/WALLY-ORI", "3000",
-    "rv64i/WALLY-XORI", "3000",
-    "rv64i/WALLY-SLTI", "3000",
-    "rv64i/WALLY-SLTIU", "3000",
-    "rv64i/WALLY-SLLI", "3000",
-    "rv64i/WALLY-SRLI", "3000",
-    "rv64i/WALLY-SRAI", "3000",
-    "rv64i/WALLY-JAL", "4000",
-    "rv64i/WALLY-JALR", "3000",
-    "rv64i/WALLY-STORE", "3000",
-    "rv64i/WALLY-ADDIW", "3000",
-    "rv64i/WALLY-SLLIW", "3000",
-    "rv64i/WALLY-SRLIW", "3000",
-    "rv64i/WALLY-SRAIW", "3000",
-    "rv64i/WALLY-ADDW", "4000",
-    "rv64i/WALLY-SUBW", "4000",
-    "rv64i/WALLY-SLLW", "3000",
-    "rv64i/WALLY-SRLW", "3000",
-    "rv64i/WALLY-SRAW", "3000",
-    "rv64i/WALLY-BEQ" ,"5000",
-    "rv64i/WALLY-BNE", "5000 ",
-    "rv64i/WALLY-BLTU", "5000 ",
-    "rv64i/WALLY-BLT", "5000",
-    "rv64i/WALLY-BGE", "5000 ",
-    "rv64i/WALLY-BGEU", "5000 ",
-    "rv64i/WALLY-CSRRW", "4000",
-    "rv64i/WALLY-CSRRS", "4000",
-    "rv64i/WALLY-CSRRC", "5000",
-    "rv64i/WALLY-CSRRWI", "4000",
-    "rv64i/WALLY-CSRRSI", "4000",
-    "rv64i/WALLY-CSRRCI", "4000"
-  };
-
-  string tests32a[] = '{
-    "rv32a/WALLY-AMO", "2110",
-    "rv32a/WALLY-LRSC", "2110"
-  };
-
-  string tests32m[] = '{
-    "rv32m/I-MUL-01", "2000",
-    "rv32m/I-MULH-01", "2000",
-    "rv32m/I-MULHSU-01", "2000",
-    "rv32m/I-MULHU-01", "2000",
-    "rv32m/I-DIV-01", "2000",
-    "rv32m/I-DIVU-01", "2000",
-    "rv32m/I-REM-01", "2000",
-    "rv32m/I-REMU-01", "2000"
-  };
-
-  string tests32ic[] = '{
-    "rv32ic/I-C-ADD-01", "2000",
-    "rv32ic/I-C-ADDI-01", "2000",
-    "rv32ic/I-C-AND-01", "2000",
-    "rv32ic/I-C-ANDI-01", "2000",
-    "rv32ic/I-C-BEQZ-01", "2000",
-    "rv32ic/I-C-BNEZ-01", "2000",
-    "rv32ic/I-C-EBREAK-01", "2000",
-    "rv32ic/I-C-J-01", "2000",
-    "rv32ic/I-C-JALR-01", "3000",
-    "rv32ic/I-C-JR-01", "3000",
-    "rv32ic/I-C-LI-01", "2000",
-    "rv32ic/I-C-LUI-01", "2000",
-    "rv32ic/I-C-LW-01", "2110",
-    "rv32ic/I-C-LWSP-01", "2110",
-    "rv32ic/I-C-MV-01", "2000",
-    "rv32ic/I-C-NOP-01", "2000",
-    "rv32ic/I-C-OR-01", "2000",
-    "rv32ic/I-C-SLLI-01", "2000",
-    "rv32ic/I-C-SRAI-01", "2000",
-    "rv32ic/I-C-SRLI-01", "2000",
-    "rv32ic/I-C-SUB-01", "2000",
-    "rv32ic/I-C-SW-01", "2000",
-    "rv32ic/I-C-SWSP-01", "2000",
-    "rv32ic/I-C-XOR-01", "2000"
-  };
-
-  string tests32iNOc[] = {
-    "rv32i/I-MISALIGN_JMP-01","2000"
-  };
-
-  string tests32i[] = {
-    //"rv32i/WALLY-PIPELINE-100K", "10a800",
-    "rv32i/I-ADD-01", "2000",
-    "rv32i/I-ADDI-01","2000",
-    "rv32i/I-AND-01","2000",
-    "rv32i/I-ANDI-01","2000",
-    "rv32i/I-AUIPC-01","2000",
-    "rv32i/I-BEQ-01","3000",
-    "rv32i/I-BGE-01","3000",
-    "rv32i/I-BGEU-01","3000",
-    "rv32i/I-BLT-01","3000",
-    "rv32i/I-BLTU-01","3000",
-    "rv32i/I-BNE-01","3000",
-    "rv32i/I-DELAY_SLOTS-01","2000",
-    "rv32i/I-EBREAK-01","2000",
-    "rv32i/I-ECALL-01","2000",
-    "rv32i/I-ENDIANESS-01","2010",
-    "rv32i/I-IO-01","2030rv",
-    "rv32i/I-JAL-01","3000",
-    "rv32i/I-JALR-01","3000",
-    "rv32i/I-LB-01","3020",
-    "rv32i/I-LBU-01","3020",
-    "rv32i/I-LH-01","3050",
-    "rv32i/I-LHU-01","3050",
-    "rv32i/I-LUI-01","2000",
-    "rv32i/I-LW-01","3110",
-    "rv32i/I-MISALIGN_LDST-01","2010",
-    "rv32i/I-NOP-01","2000",
-    "rv32i/I-OR-01","2000",
-    "rv32i/I-ORI-01","2000",
-    "rv32i/I-RF_size-01","2000",
-    "rv32i/I-RF_width-01","2000",
-    "rv32i/I-RF_x0-01","2010",
-    "rv32i/I-SB-01","3000",
-    "rv32i/I-SH-01","3000",
-    "rv32i/I-SLL-01","2000",
-    "rv32i/I-SLLI-01","2000",
-    "rv32i/I-SLT-01","2000",
-    "rv32i/I-SLTI-01","2000",
-    "rv32i/I-SLTIU-01","2000",
-    "rv32i/I-SLTU-01","2000",
-    "rv32i/I-SRA-01","2000",
-    "rv32i/I-SRAI-01","2000",
-    "rv32i/I-SRL-01","2000",
-    "rv32i/I-SRLI-01","2000",
-    "rv32i/I-SUB-01","2000",
-    "rv32i/I-SW-01","3000",
-    "rv32i/I-XOR-01","2000",
-    "rv32i/I-XORI-01","2000",
-    "rv32i/WALLY-ADD", "3000",
-    "rv32i/WALLY-SUB", "3000",
-    "rv32i/WALLY-ADDI", "2000",
-    "rv32i/WALLY-ANDI", "2000",
-    "rv32i/WALLY-ORI", "2000",
-    "rv32i/WALLY-XORI", "2000",
-    "rv32i/WALLY-SLTI", "2000",
-    "rv32i/WALLY-SLTIU", "2000",
-    "rv32i/WALLY-SLLI", "2000",
-    "rv32i/WALLY-SRLI", "2000",
-    "rv32i/WALLY-SRAI", "2000",
-    "rv32i/WALLY-LOAD", "11c00",
-    "rv32i/WALLY-SUB", "3000",
-    "rv32i/WALLY-STORE", "2000",
-    "rv32i/WALLY-JAL", "3000",
-    "rv32i/WALLY-JALR", "2000",
-    "rv32i/WALLY-BEQ" ,"4000",
-    "rv32i/WALLY-BNE", "4000 ",
-    "rv32i/WALLY-BLTU", "4000 ",
-    "rv32i/WALLY-BLT", "4000",
-    "rv32i/WALLY-BGE", "4000 ",
-    "rv32i/WALLY-BGEU", "4000 ",
-    "rv32i/WALLY-CSRRW", "3000",
-    "rv32i/WALLY-CSRRS", "3000",
-    "rv32i/WALLY-CSRRC", "4000",
-    "rv32i/WALLY-CSRRWI", "3000",
-    "rv32i/WALLY-CSRRSI", "3000",
-    "rv32i/WALLY-CSRRCI", "3000"
-  };
-
-  string testsBP64[] = '{
-    "rv64BP/blink-led", "10000"
-/* -----\/----- EXCLUDED -----\/-----
-    "rv64BP/simple", "10000",
-    "rv64BP/mmm", "1000000",
-    "rv64BP/linpack_bench", "1000000",
-    "rv64BP/sieve", "1000000",
-    "rv64BP/qsort", "1000000",
-    "rv64BP/dhrystone", "1000000"
- -----/\----- EXCLUDED -----/\----- */
-  };
-
-  string tests64p[] = '{
-    "rv64p/WALLY-MSTATUS", "2000",
-    "rv64p/WALLY-MCAUSE", "3000",
-    "rv64p/WALLY-SCAUSE", "2000",
-    "rv64p/WALLY-MEPC", "5000",
-    "rv64p/WALLY-SEPC", "4000",
-    "rv64p/WALLY-MTVAL", "6000",
-    "rv64p/WALLY-STVAL", "4000",
-    "rv64p/WALLY-MTVEC", "2000",
-    "rv64p/WALLY-STVEC", "2000",
-    "rv64p/WALLY-MARCHID", "4000",
-    "rv64p/WALLY-MIMPID", "4000",
-    "rv64p/WALLY-MHARTID", "4000",
-    "rv64p/WALLY-MVENDORID", "4000",
-    "rv64p/WALLY-MIE", "3000",
-    "rv64p/WALLY-MEDELEG", "4000",
-    "rv64p/WALLY-IP", "2000",
-    "rv64p/WALLY-CSR-PERMISSIONS-M", "5000",
-    "rv64p/WALLY-CSR-PERMISSIONS-S", "3000"
-  };
-
-  string tests32p[] = '{
-    "rv32p/WALLY-MSTATUS", "2000",
-    "rv32p/WALLY-MCAUSE", "3000",
-    "rv32p/WALLY-SCAUSE", "2000",
-    "rv32p/WALLY-MEPC", "5000",
-    "rv32p/WALLY-SEPC", "4000",
-    "rv32p/WALLY-MTVAL", "5000",
-    "rv32p/WALLY-STVAL", "4000",
-    "rv32p/WALLY-MARCHID", "4000",
-    "rv32p/WALLY-MIMPID", "4000",
-    "rv32p/WALLY-MHARTID", "4000",
-    "rv32p/WALLY-MVENDORID", "4000",
-    "rv32p/WALLY-MTVEC", "2000",
-    "rv32p/WALLY-STVEC", "2000",
-    "rv32p/WALLY-MIE", "3000",
-    "rv32p/WALLY-MEDELEG", "4000",
-    "rv32p/WALLY-IP", "3000",
-    "rv32p/WALLY-CSR-PERMISSIONS-M", "5000",
-    "rv32p/WALLY-CSR-PERMISSIONS-S", "3000"
-  };
-
-  string tests64periph[] = '{
-    "rv64i-periph/WALLY-PERIPH", "2000"
-  };
-
-  string tests32periph[] = '{
-    "rv32i-periph/WALLY-PLIC", "2080"
-  };
-
-   string tests[];
   string ProgramAddrMapFile, ProgramLabelMapFile;
   logic [`AHBW-1:0] HRDATAEXT;
-  logic             HREADYEXT, HRESPEXT, HREADY;
-  logic 	    HSELEXT;
-  
+  logic             HREADYEXT, HRESPEXT;
   logic [31:0]      HADDR;
   logic [`AHBW-1:0] HWDATA;
   logic             HWRITE;
@@ -524,97 +67,53 @@ string tests32f[] = '{
 
   logic 	    DCacheFlushDone, DCacheFlushStart;
     
-  flopenr #(`XLEN) PCWReg(clk, reset, ~dut.wallypipelinedsoc.core.ieu.dp.StallW, dut.wallypipelinedsoc.core.ifu.PCM, PCW);
-  flopenr  #(32)   InstrWReg(clk, reset, ~dut.wallypipelinedsoc.core.ieu.dp.StallW,  dut.wallypipelinedsoc.core.ifu.InstrM, InstrW);
+  flopenr #(`XLEN) PCWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.PCM, PCW);
+  flopenr  #(32)   InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW,  dut.core.ifu.InstrM, InstrW);
 
   // check assertions for a legal configuration
   riscvassertions riscvassertions();
-  logging logging(clk, reset, dut.wallypipelinedsoc.uncore.HADDR, dut.wallypipelinedsoc.uncore.HTRANS);
 
-  // pick tests based on modes supported
-  initial begin
-    if (`XLEN == 64) begin // RV64
-      if (`TESTSBP) begin
-        tests = testsBP64;
-	// testsbp should not run the other tests. It starts at address 0 rather than
-	// 0x8000_0000, the next if must remain an else if.	
-      end else if (TESTSPERIPH)
-        tests = tests64periph;
-      else if (TESTSPRIV)
-        tests = tests64p;
-      else begin
-        tests = {tests64p,tests64i, tests64periph};
-        if (`C_SUPPORTED) tests = {tests, tests64ic};
-        else              tests = {tests, tests64iNOc};
-        if (`M_SUPPORTED) tests = {tests, tests64m};
-        if (`F_SUPPORTED) tests = {tests64f, tests};
-        if (`D_SUPPORTED) tests = {tests64d, tests};
-        if (`VIRTMEM_SUPPORTED) tests = {tests64mmu, tests};
-        if (`A_SUPPORTED) tests = {tests64a, tests};
-      end
-      //tests = {tests64a, tests};
-    end else begin // RV32
-      // *** add the 32 bit bp tests
-      if (TESTSPERIPH)
-        tests = tests32periph;
-      else if (TESTSPRIV)
-        tests = tests32p;
-      else begin
-          tests = {tests32i, tests32p};//,tests32periph}; *** broken at the moment
-          if (`C_SUPPORTED % 2 == 1) tests = {tests, tests32ic};    
-          else                       tests = {tests, tests32iNOc};
-          if (`M_SUPPORTED % 2 == 1) tests = {tests, tests32m};
-          if (`F_SUPPORTED) tests = {tests32f, tests};
-          if (`VIRTMEM_SUPPORTED) tests = {tests32mmu, tests};
-          if (`A_SUPPORTED) tests = {tests32a, tests};
-     end
-    end
-  end
+  string signame, memfilename, pathname, romfilename, sdcfilename;
 
-  string signame, memfilename, romfilename, sdcfilename;
-
-  logic [3:0] GPIOPinsIn_IO;
-  logic [4:0] GPIOPinsOut_IO;
+  logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
   logic UARTSin, UARTSout;
-  logic ddr4_calib_complete;
+
   
 
   logic SDCCLK;
-  tri1 SDCCmd;
-  tri1 [3:0] SDCDat;
   logic      SDCCmdIn;
   logic      SDCCmdOut;
   logic      SDCCmdOE;
   logic [3:0] SDCDatIn;
+  tri1 [3:0] SDCDat;
+  tri1 SDCCmd;
 
-  assign SDCCmd = SDCCmdOE ? SDCCmdOut : 1'bz;
-  assign SDCCmdIn = SDCCmd;
-  assign SDCDatIn = SDCDat;
-    
+  logic             HREADY;
+  logic 	    HSELEXT;
+  
   sdModel sdcard
     (.sdClk(SDCCLK),
     .cmd(SDCCmd), 
     .dat(SDCDat));
 
+  assign SDCCmd = SDCCmdOE ? SDCCmdOut : 1'bz;
+  assign SDCCmdIn = SDCCmd;
+  assign SDCDatIn = SDCDat;
+
   // instantiate device to be tested
   assign GPIOPinsIn = 0;
   assign UARTSin = 1;
- 
-  ram #(.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) 
-  ram (.HCLK, .HRESETn, .HADDR, .HWRITE, .HTRANS, .HWDATA, .HSELTim(HSELEXT), 
-        .HREADTim(HRDATAEXT), .HREADYTim(HREADYEXT), .HRESPTim(HRESPEXT));
- 
 
-  wallypipelinedsocwrapper dut(.clk, .reset_ext, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
+  wallypipelinedsoc dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
                         .HCLK, .HRESETn, .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT,
-                        .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(0), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn,
+                        .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn,
                         .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); 
 
   // Track names of instructions
-  instrTrackerTB it(clk, reset, dut.wallypipelinedsoc.core.ieu.dp.FlushE,
-                dut.wallypipelinedsoc.core.ifu.icache.FinalInstrRawF,
-                dut.wallypipelinedsoc.core.ifu.InstrD, dut.wallypipelinedsoc.core.ifu.InstrE,
-                dut.wallypipelinedsoc.core.ifu.InstrM,  InstrW,
+  instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE,
+                dut.core.ifu.FinalInstrRawF[31:0],
+                dut.core.ifu.InstrD, dut.core.ifu.InstrE,
+                dut.core.ifu.InstrM,  InstrW,
                 InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
 
   // initialize tests
@@ -623,58 +122,52 @@ string tests32f[] = '{
 
   initial
     begin
-      test = 0;
+      test = 1;
       totalerrors = 0;
       testadr = 0;
+      testadrNoBase = 0;
       // fill memory with defined values to reduce Xs in simulation
       // Quick note the memory will need to be initialized.  The C library does not
       //  guarantee the  initialized reads.  For example a strcmp can read 6 byte
       //  strings, but uses a load double to read them in.  If the last 2 bytes are
       //  not initialized the compare results in an 'x' which propagates through 
       // the design.
-      if (`XLEN == 32) meminit = 32'hFEDC0123;
-      else meminit = 64'hFEDCBA9876543210;
-      // *** broken because DTIM also drives RAM
-/* -----\/----- EXCLUDED -----\/-----
-      if (`TESTSBP) begin
-	for (i=MemStartAddr; i<MemEndAddr; i = i+1) begin
-	  ram.RAM[i] = meminit;
-	end
-      end
- -----/\----- EXCLUDED -----/\----- */
+      if (TEST == "coremark") 
+
       // read test vectors into memory
-      memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"};
-      //romfilename = {"../../testsBP/fpga-test-sdc/bin/fpga-test-sdc.hex"};
+      pathname = tvpaths[tests[0].atoi()];
+/*      if (tests[0] == `IMPERASTEST)
+        pathname = tvpaths[0];
+      else pathname = tvpaths[1]; */
+      memfilename = {pathname, tests[test], ".elf.memfile"};
       romfilename = {"../../tests/testsBP/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
-      sdcfilename = {"../src/sdc/tb/ramdisk2.hex"};      
-      $readmemh(memfilename, ram.RAM);
-      $readmemh(romfilename, dut.wallypipelinedsoc.uncore.bootram.bootram.RAM);
+      sdcfilename = {"../testbench/sdc/ramdisk2.hex"};      
+      //$readmemh(romfilename, dut.wallypipelinedsoc.uncore.bootrom.bootrom.memory.RAM);
       $readmemh(sdcfilename, sdcard.FLASHmem);
-      ProgramAddrMapFile = {"../../imperas-riscv-tests/work/rv64BP/fpga-test-sdc.objdump.addr"};
-      ProgramLabelMapFile = {"../../imperas-riscv-tests/work/rv64BP/fpga-test-sdc.objdump.lab"};
+
+      ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
+      ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
       $display("Read memfile %s", memfilename);
-      reset = 0; #97; reset = 1; # 1000; reset = 0;
+      reset_ext = 0; #97 reset_ext = 1; # 1000; reset_ext = 0;
     end
 
   // generate clock to sequence tests
   always
     begin
       clk = 1; # 5; clk = 0; # 5;
+      // if ($time % 100000 == 0) $display("Time is %0t", $time);
     end
    
   // check results
   always @(negedge clk)
     begin    
-/* -----\/----- EXCLUDED -----\/-----
-      if (dut.wallypipelinedsoc.core.priv.EcallFaultM & 
-			    (dut.wallypipelinedsoc.core.ieu.dp.regf.rf[3] == 1 | 
-			     (dut.wallypipelinedsoc.core.ieu.dp.regf.we3 & 
-			      dut.wallypipelinedsoc.core.ieu.dp.regf.a3 == 3 & 
-			      dut.wallypipelinedsoc.core.ieu.dp.regf.wd3 == 1))) begin
- -----/\----- EXCLUDED -----/\----- */
+      if (TEST == "coremark")
+        if (dut.core.priv.priv.ecallM) begin
+          $display("Benchmark: coremark is done.");
+          $stop;
+        end
       if (DCacheFlushDone) begin
-        //$display("Code ended with ecall with gp = 1");
-
+ 
         #600; // give time for instructions in pipeline to finish
         // clear signature to prevent contamination from previous tests
         for(i=0; i<SIGNATURESIZE; i=i+1) begin
@@ -682,7 +175,7 @@ string tests32f[] = '{
         end
 
         // read signature, reformat in 64 bits if necessary
-        signame = {"../../imperas-riscv-tests/work/", tests[test], ".signature.output"};
+        signame = {pathname, tests[test], ".signature.output"};
         $readmemh(signame, sig32);
         i = 0;
         while (i < SIGNATURESIZE) begin
@@ -693,8 +186,8 @@ string tests32f[] = '{
             signature[i/2] = {sig32[i+1], sig32[i]};
             i = i + 2;
           end
-          if (sig32[i-1] === 'bx) begin
-            if (i == 1) begin
+          if (i >= 4 & sig32[i-4] === 'bx) begin
+            if (i == 4) begin
               i = SIGNATURESIZE+1; // flag empty file
               $display("  Error: empty test file");
             end else i = SIGNATURESIZE; // skip over the rest of the x's for efficiency
@@ -705,17 +198,27 @@ string tests32f[] = '{
         errors = (i == SIGNATURESIZE+1); // error if file is empty
         i = 0;
         testadr = (`RAM_BASE+tests[test+1].atohex())/(`XLEN/8);
+        testadrNoBase = (tests[test+1].atohex())/(`XLEN/8);
         /* verilator lint_off INFINITELOOP */
         while (signature[i] !== 'bx) begin
-          //$display("signature[%h] = %h", i, signature[i]);
-          if (signature[i] !== ram.RAM[testadr+i] &
-	      (signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin
-            if (signature[i+4] !== 'bx | signature[i] !== 32'hFFFFFFFF) begin
+          logic [`XLEN-1:0] sig;
+/* -----\/----- EXCLUDED -----\/-----
+          if (`DMEM == `MEM_TIM) sig = dut.core.lsu.dtim.dtim.ram.memory.RAM[testadrNoBase+i];
+          else                   sig = dut.uncore.ram.ram.memory.RAM[testadrNoBase+i];
+ -----/\----- EXCLUDED -----/\----- */
+          //$display("signature[%h] = %h sig = %h", i, signature[i], sig);
+          if (signature[i] !== sig &
+          //if (signature[i] !== dut.core.lsu.dtim.ram.memory.RAM[testadr+i] &
+	      (signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin  // ***i+1?
+            if ((signature[i] !== '0 | signature[i+4] !== 'x)) begin
+//            if (signature[i+4] !== 'bx | (signature[i] !== 32'hFFFFFFFF & signature[i] !== 32'h00000000)) begin
               // report errors unless they are garbage at the end of the sim
               // kind of hacky test for garbage right now
+              $display("sig4 = %h ne %b", signature[i+4], signature[i+4] !== 'bx);
               errors = errors+1;
-              $display("  Error on test %s result %d: adr = %h sim (D$) %h sim (TIM) = %h, signature = %h", 
-                    tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], ram.RAM[testadr+i], signature[i]);
+              $display("  Error on test %s result %d: adr = %h sim (D$) %h sim (DMEM) = %h, signature = %h", 
+                    tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]);
+                    //   tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], dut.core.lsu.dtim.ram.memory.RAM[testadr+i], signature[i]);
               $stop;//***debug
             end
           end
@@ -736,51 +239,66 @@ string tests32f[] = '{
           $stop;
         end
         else begin
-          memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"};
-          $readmemh(memfilename, ram.RAM);
-          $display("Read memfile %s", memfilename);
-	  ProgramAddrMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.addr"};
-	  ProgramLabelMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.lab"};
-	  reset = 0; #97; reset = 1; # 1000; reset = 0;
+            //pathname = tvpaths[tests[0]];
+            memfilename = {pathname, tests[test], ".elf.memfile"};
+            //$readmemh(memfilename, dut.uncore.ram.ram.memory.RAM);
+/* -----\/----- EXCLUDED -----\/-----
+            if (`IMEM == `MEM_TIM) $readmemh(memfilename, dut.core.ifu.irom.irom.ram.memory.RAM);
+            else                   $readmemh(memfilename, dut.uncore.ram.ram.memory.RAM);
+            if (`DMEM == `MEM_TIM) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.memory.RAM);
+ -----/\----- EXCLUDED -----/\----- */
+
+            ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
+            ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
+            $display("Read memfile %s", memfilename);
+            reset_ext = 1; # 47; reset_ext = 0;
         end
       end
     end // always @ (negedge clk)
 
   // track the current function or global label
-/* -----\/----- EXCLUDED -----\/-----
   if (DEBUG == 1) begin : FunctionName
     FunctionName FunctionName(.reset(reset),
 			      .clk(clk),
 			      .ProgramAddrMapFile(ProgramAddrMapFile),
 			      .ProgramLabelMapFile(ProgramLabelMapFile));
   end
- -----/\----- EXCLUDED -----/\----- */
 
-  assign DCacheFlushStart = dut.wallypipelinedsoc.core.priv.EcallFaultM & 
-			    (dut.wallypipelinedsoc.core.ieu.dp.regf.rf[3] == 1 | 
-			     (dut.wallypipelinedsoc.core.ieu.dp.regf.we3 & 
-			      dut.wallypipelinedsoc.core.ieu.dp.regf.a3 == 3 & 
-			      dut.wallypipelinedsoc.core.ieu.dp.regf.wd3 == 1));
-  
+  // Termination condition
+  // terminate on a specific ECALL after li x3,1 for old Imperas tests,  *** remove this when old imperas tests are removed
+  // or sw	gp,-56(t0) for new Imperas tests
+  // or sd gp, -56(t0) 
+  // or on a jump to self infinite loop (6f) for RISC-V Arch tests
+  logic ecf; // remove this once we don't rely on old Imperas tests with Ecalls
+  if (`ZICSR_SUPPORTED) assign ecf = dut.core.priv.priv.EcallFaultM;
+  else                  assign ecf = 0;
+  assign DCacheFlushStart = ecf & 
+			    (dut.core.ieu.dp.regf.rf[3] == 1 | 
+			     (dut.core.ieu.dp.regf.we3 & 
+			      dut.core.ieu.dp.regf.a3 == 3 & 
+			      dut.core.ieu.dp.regf.wd3 == 1)) |
+          (dut.core.ifu.InstrM == 32'h6f | dut.core.ifu.InstrM == 32'hfc32a423 | dut.core.ifu.InstrM == 32'hfc32a823) & dut.core.ieu.c.InstrValidM;
+
   DCacheFlushFSM DCacheFlushFSM(.clk(clk),
-				.reset(reset),
-				.start(DCacheFlushStart),
-				.done(DCacheFlushDone));
-  
+    			.reset(reset),
+	    		.start(DCacheFlushStart),
+		    	.done(DCacheFlushDone));
 
   // initialize the branch predictor
-  if (`BPRED_ENABLED == 1)
+  if (`BPRED_ENABLED == 1) 
     initial begin
-      $readmemb(`TWO_BIT_PRELOAD, dut.wallypipelinedsoc.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
-      $readmemb(`BTB_PRELOAD, dut.wallypipelinedsoc.core.ifu.bpred.bpred.TargetPredictor.memory.mem);
-    end
+      $readmemb(`TWO_BIT_PRELOAD, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
+      $readmemb(`BTB_PRELOAD, dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem);    
+    end 
 endmodule
 
-module riscvassertions();
-  // Legal number of PMP entries are 0, 16, or 64
+module riscvassertions;
   initial begin
     assert (`PMP_ENTRIES == 0 | `PMP_ENTRIES==16 | `PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64");
-    assert (`F_SUPPORTED | ~`D_SUPPORTED) else $error("Can't support double without supporting float");
+    assert (`S_SUPPORTED | `VIRTMEM_SUPPORTED == 0) else $error("Virtual memory requires S mode support");
+    assert (`DIV_BITSPERCYCLE == 1 | `DIV_BITSPERCYCLE==2 | `DIV_BITSPERCYCLE==4) else $error("Illegal number of divider bits/cycle: DIV_BITSPERCYCLE must be 1, 2, or 4");
+    assert (`F_SUPPORTED | ~`D_SUPPORTED) else $error("Can't support double (D) without supporting float (F)");
+    assert (`I_SUPPORTED ^ `E_SUPPORTED) else $error("Exactly one of I and E must be supported");
     assert (`XLEN == 64 | ~`D_SUPPORTED) else $error("Wally does not yet support D extensions on RV32");
     assert (`DCACHE_WAYSIZEINBYTES <= 4096 | (`DMEM != `MEM_CACHE) | `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
     assert (`DCACHE_LINELENINBITS >= 128 | (`DMEM != `MEM_CACHE)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled");
@@ -788,14 +306,21 @@ module riscvassertions();
     assert (`ICACHE_WAYSIZEINBYTES <= 4096 | (`IMEM != `MEM_CACHE) | `VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
     assert (`ICACHE_LINELENINBITS >= 32 | (`IMEM != `MEM_CACHE)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled");
     assert (`ICACHE_LINELENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size");
-    assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS) else $error("DCACHE_LINELENINBITS must be a power of 2");
-    assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2");
-    assert (2**$clog2(`ICACHE_LINELENINBITS) == `ICACHE_LINELENINBITS) else $error("ICACHE_LINELENINBITS must be a power of 2");
-    assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2");
-    assert (`ICACHE_NUMWAYS == 1 | (`IMEM != `MEM_CACHE)) else $warning("Multiple Instruction Cache ways not yet implemented");
-    assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES) else $error("ITLB_ENTRIES must be a power of 2");
-    assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES) else $error("DTLB_ENTRIES must be a power of 2");
-    assert (`RAM_RANGE >= 56'h07FFFFFF) else $error("Some regression tests will fail if RAM_RANGE is less than 56'h07FFFFFF");
+    assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS | (`DMEM != `MEM_CACHE)) else $error("DCACHE_LINELENINBITS must be a power of 2");
+    assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES | (`DMEM != `MEM_CACHE)) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2");
+    assert (2**$clog2(`ICACHE_LINELENINBITS) == `ICACHE_LINELENINBITS | (`IMEM != `MEM_CACHE)) else $error("ICACHE_LINELENINBITS must be a power of 2");
+    assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES | (`IMEM != `MEM_CACHE)) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2");
+    assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES | `VIRTMEM_SUPPORTED==0) else $error("ITLB_ENTRIES must be a power of 2");
+    assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES | `VIRTMEM_SUPPORTED==0) else $error("DTLB_ENTRIES must be a power of 2");
+    assert (`RAM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if RAM_RANGE is less than 56'h07FFFFFF");
+	  assert (`ZICSR_SUPPORTED == 1 | (`PMP_ENTRIES == 0 & `VIRTMEM_SUPPORTED == 0)) else $error("PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported.");
+    assert (`ZICSR_SUPPORTED == 1 | (`S_SUPPORTED == 0 & `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZISR not supported");
+    assert (`U_SUPPORTED | (`S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported");
+//    assert (`MEM_DCACHE == 0 | `MEM_DTIM == 0) else $error("Can't simultaneously have a data cache and TIM");
+    assert (`DMEM == `MEM_CACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache");
+    assert (`IMEM == `MEM_CACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache");
+    assert (`DMEM == `MEM_CACHE | `DBUS ==0) else $error("Dcache rquires DBUS.");
+    assert (`IMEM == `MEM_CACHE | `IBUS ==0) else $error("Icache rquires IBUS.");    
   end
 endmodule
 
@@ -809,70 +334,70 @@ module DCacheFlushFSM
    input logic start,
    output logic done);
 
-  localparam integer numlines = testbench.dut.wallypipelinedsoc.core.lsu.bus.dcache.NUMLINES;
-  localparam integer numways = testbench.dut.wallypipelinedsoc.core.lsu.bus.dcache.NUMWAYS;
-  localparam integer linebytelen = testbench.dut.wallypipelinedsoc.core.lsu.bus.dcache.LINEBYTELEN;
-  localparam integer numwords = testbench.dut.wallypipelinedsoc.core.lsu.bus.dcache.LINELEN/`XLEN;  
-  localparam integer lognumlines = $clog2(numlines);
-  localparam integer loglinebytelen = $clog2(linebytelen);
-  localparam integer lognumways = $clog2(numways);
-  localparam integer tagstart = lognumlines + loglinebytelen;
-
-
-
-  genvar index, way, cacheWord;
-  logic [`XLEN-1:0]  CacheData [numways-1:0] [numlines-1:0] [numwords-1:0];
-  logic [`XLEN-1:0]  CacheTag [numways-1:0] [numlines-1:0] [numwords-1:0];
-  logic CacheValid  [numways-1:0] [numlines-1:0] [numwords-1:0];
-  logic CacheDirty  [numways-1:0] [numlines-1:0] [numwords-1:0];
-  logic [`PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [numwords-1:0];
   genvar adr;
 
   logic [`XLEN-1:0] ShadowRAM[`RAM_BASE>>(1+`XLEN/32):(`RAM_RANGE+`RAM_BASE)>>1+(`XLEN/32)];
   
-  for(index = 0; index < numlines; index++) begin
-    for(way = 0; way < numways; way++) begin
-      for(cacheWord = 0; cacheWord < numwords; cacheWord++) begin
-        copyShadow #(.tagstart(tagstart), .loglinebytelen(loglinebytelen))
-        copyShadow(.clk,
-            .start,
-            .tag(testbench.dut.wallypipelinedsoc.core.lsu.bus.dcache.CacheWays[way].CacheTagMem.StoredData[index]),
-            .valid(testbench.dut.wallypipelinedsoc.core.lsu.bus.dcache.CacheWays[way].ValidBits[index]),
-            .dirty(testbench.dut.wallypipelinedsoc.core.lsu.bus.dcache.CacheWays[way].DirtyBits[index]),
-            .data(testbench.dut.wallypipelinedsoc.core.lsu.bus.dcache.CacheWays[way].word[cacheWord].CacheDataMem.StoredData[index]),
-            .index(index),
-            .cacheWord(cacheWord),
-            .CacheData(CacheData[way][index][cacheWord]),
-            .CacheAdr(CacheAdr[way][index][cacheWord]),
-            .CacheTag(CacheTag[way][index][cacheWord]),
-            .CacheValid(CacheValid[way][index][cacheWord]),
-            .CacheDirty(CacheDirty[way][index][cacheWord]));
-      end
-    end
-  end
+	if(`DMEM == `MEM_CACHE) begin
+	  localparam integer numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES;
+	  localparam integer numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS;
+	  localparam integer linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN;
+	  localparam integer numwords = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN/`XLEN;  
+	  localparam integer lognumlines = $clog2(numlines);
+	  localparam integer loglinebytelen = $clog2(linebytelen);
+	  localparam integer lognumways = $clog2(numways);
+	  localparam integer tagstart = lognumlines + loglinebytelen;
 
-  integer i, j, k;
-  
-  always @(posedge clk) begin
-    if (start) begin #1
-      #1
-      for(i = 0; i < numlines; i++) begin
-	for(j = 0; j < numways; j++) begin
-	  for(k = 0; k < numwords; k++) begin
-	  if (CacheValid[j][i][k] & CacheDirty[j][i][k]) begin
-	    ShadowRAM[CacheAdr[j][i][k] >> $clog2(`XLEN/8)] = CacheData[j][i][k];
-	    end
-	  end	
+
+
+	  genvar 			 index, way, cacheWord;
+	  logic [`XLEN-1:0]  CacheData [numways-1:0] [numlines-1:0] [numwords-1:0];
+	  logic [`XLEN-1:0]  CacheTag [numways-1:0] [numlines-1:0] [numwords-1:0];
+	  logic 			 CacheValid  [numways-1:0] [numlines-1:0] [numwords-1:0];
+	  logic 			 CacheDirty  [numways-1:0] [numlines-1:0] [numwords-1:0];
+	  logic [`PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [numwords-1:0];
+      for(index = 0; index < numlines; index++) begin
+		for(way = 0; way < numways; way++) begin
+		  for(cacheWord = 0; cacheWord < numwords; cacheWord++) begin
+			copyShadow #(.tagstart(tagstart),
+						 .loglinebytelen(loglinebytelen))
+			copyShadow(.clk,
+					   .start,
+					   .tag(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.StoredData[index]),
+					   .valid(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].ValidBits[index]),
+					   .dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].DirtyBits[index]),
+					   .data(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].word[cacheWord].CacheDataMem.StoredData[index]),
+					   .index(index),
+					   .cacheWord(cacheWord),
+					   .CacheData(CacheData[way][index][cacheWord]),
+					   .CacheAdr(CacheAdr[way][index][cacheWord]),
+					   .CacheTag(CacheTag[way][index][cacheWord]),
+					   .CacheValid(CacheValid[way][index][cacheWord]),
+					   .CacheDirty(CacheDirty[way][index][cacheWord]));
+		  end
+		end
+      end
+
+	  integer i, j, k;
+
+	  always @(posedge clk) begin
+		if (start) begin #1
+		  #1
+			for(i = 0; i < numlines; i++) begin
+			  for(j = 0; j < numways; j++) begin
+				for(k = 0; k < numwords; k++) begin
+				  if (CacheValid[j][i][k] & CacheDirty[j][i][k]) begin
+					ShadowRAM[CacheAdr[j][i][k] >> $clog2(`XLEN/8)] = CacheData[j][i][k];
+				  end
+				end	
+			  end
+			end
+		end
+	  end
+
+	  
 	end
-      end
-    end
-  end
-
-
-  flop #(1) doneReg(.clk(clk),
-		    .d(start),
-		    .q(done));
-		    
+  flop #(1) doneReg(.clk, .d(start), .q(done));
 endmodule
 
 module copyShadow
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefile b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefile
index e177848b..095f81ff 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefile
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefile
@@ -1,3 +1,5 @@
 include ../../Makefile.include
 
+RVTEST_DEFINES += -march=rv$(XLEN)ia # KMG: removed compressed instructions from privileged tests
+
 $(eval $(call compile_template,-march=rv32iac -mabi=ilp32 -Drvtest_mtrap_routine=True -DXLEN=$(XLEN)))
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-mtvec-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-mtvec-01.reference_output
new file mode 100644
index 00000000..4e523b01
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-mtvec-01.reference_output
@@ -0,0 +1,1025 @@
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-stvec-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-stvec-01.reference_output
new file mode 100644
index 00000000..bc760ed6
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-stvec-01.reference_output
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output
new file mode 100644
index 00000000..faac488f
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output
@@ -0,0 +1,990 @@
+00000aaa # Test 5.3.1.4: readback value from writing mie to enable interrupts
+00000001 # mcause from an instruction access fault
+00000000 # mtval of faulting instruction address (0x0)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000002 # mcause from an Illegal instruction
+00000000 # mtval of faulting instruction (0x0)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000003 # mcause from Breakpoint
+800003ec # mtval of breakpoint instruction adress (0x800003ec)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000004 # mcause from load address misaligned
+800003f5 # mtval of misaligned address (0x800003f5)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000005 # mcause from load access
+00000000 # mtval of accessed adress (0x0)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000006 # mcause from store misaligned
+80000411 # mtval of address with misaligned store instr (0x80000410)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000007 # mcause from store access
+00000000 # mtval of accessed address (0x0)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+0000000b # mcause from M mode ecall 
+00000000 # mtval of ecall (*** defined to be zero for now)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000008 # mcause from U mode ecall 
+00000000 # mtval of ecall (*** defined to be zero for now)
+00000080 # masked out mstatus.MPP = 00 (from U mode), mstatus.MPIE = 1, and mstatus.MIE = 0
+00000009 # mcause from S mode ecall 
+00000000 # mtval of ecall (*** defined to be zero for now)
+00000880 # masked out mstatus.MPP = 01 (from S mode), mstatus.MPIE = 1, and mstatus.MIE = 0
+000007ec # value to indicate a vectored interrupts
+80000007 # mcause value from m time interrupt
+00000000 # mtval for mtime interrupt (0x0)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+000007ec # value to indicate a vectored interrupts
+80000001 # mcause value from m soft interrupt
+00000000 # mtval for msoft interrupt (0x0)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+000007ec # value to indicate a vectored interrupts
+8000000b # mcause value from m ext interrupt
+00000000 # mtval for mext interrupt (0x0)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+0000b309 # medeleg after attempted write of all 1's (only some bits are writeable)
+00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
+00000001 # Test 5.3.1.4: mcause from an instruction access fault
+00000000 # mtval of faulting instruction address (0x0)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000002 # mcause from an Illegal instruction
+00000000 # mtval of faulting instruction (0x0)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000003 # mcause from Breakpoint
+800003ec # mtval of breakpoint instruction adress (0x800003ec)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000004 # mcause from load address misaligned
+800003f5 # mtval of misaligned address (0x800003f5)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000005 # mcause from load access
+00000000 # mtval of accessed adress (0x0)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000006 # mcause from store misaligned
+80000411 # mtval of address with misaligned store instr (0x80000410)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000007 # mcause from store access
+00000000 # mtval of accessed address (0x0)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+0000000b # mcause from M mode ecall 
+00000000 # mtval of ecall (*** defined to be zero for now)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+000007ec # value to indicate a vectored interrupts
+80000007 # mcause value from  time interrupt
+00000000 # mtval for mtime interrupt (0x0)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+000007ec # value to indicate a vectored interrupts
+80000001 # mcause value from m soft interrupt
+00000000 # mtval for msoft interrupt (0x0)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+000007ec # value to indicate a vectored interrupts
+0000000b # mcause value from m ext interrupt
+00000000 # mtval for mext interrupt (0x0)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+0000000b # mcause from M mode ecall from test termination
+00000000 # mtval of ecall (*** defined to be zero for now)
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output
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index 00000000..bc760ed6
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-CSR-permission-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-CSR-permission-s-01.S
index 522fb6d0..1df8fa24 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-CSR-permission-s-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-CSR-permission-s-01.S
@@ -25,7 +25,7 @@
 
 INIT_TESTS
 
-s_file_begin:
+TRAP_HANDLER m
 
 # Test 5.2.3.6: Test that all the machine mode CSR's are innaccessible for reads and writes in S mode.
 
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-CSR-permission-u-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-CSR-permission-u-01.S
index 9e40fd18..b7d3a78f 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-CSR-permission-u-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-CSR-permission-u-01.S
@@ -25,7 +25,7 @@
 
 INIT_TESTS
 
-s_file_begin:
+TRAP_HANDLER m
 
 # Test 5.2.3.6: Test that all the machine mode CSR's are innaccessible for reads and writes in R mode.
 
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-MMU-SV32.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-MMU-SV32.S
index e573ed10..b9124d0c 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-MMU-SV32.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-MMU-SV32.S
@@ -25,7 +25,8 @@
 
 INIT_TESTS
 
-s_file_begin:
+TRAP_HANDLER m
+
 j test_loop_setup // begin test loop/table tests instead of executing inline code.
 
 INIT_TEST_TABLE
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PMA.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PMA.S
index f9dbe8d5..98d5e013 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PMA.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PMA.S
@@ -38,7 +38,8 @@
 
 INIT_TESTS
 
-s_file_begin:
+TRAP_HANDLER m
+
 j test_loop_setup // begin test loop/table tests instead of executing inline code.
 
 INIT_TEST_TABLE
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PMP.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PMP.S
index d1d02cf2..f1bf5e91 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PMP.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PMP.S
@@ -25,7 +25,8 @@
 
 INIT_TESTS
 
-s_file_begin:
+TRAP_HANDLER m
+
 j test_loop_setup // begin test loop/table tests instead of executing inline code.
 
 INIT_TEST_TABLE
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
index aa72d5b1..2400173b 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h
@@ -52,16 +52,128 @@ RVTEST_CODE_BEGIN
     // address for stack
     la sp, top_of_stack
 
-    // trap handler setup
-    la x1, machine_trap_handler
-    csrrw x4, mtvec, x1  // x4 reserved for "default" trap handler address that needs to be restored before halting this test.
+.endm
+
+// Code to trigger traps goes here so we have consistent mtvals for instruction adresses
+// Even if more tests are added.  
+.macro CAUSE_TRAP_TRIGGERS
+j end_trap_triggers
+
+// The following tests involve causing many of the interrupts and exceptions that are easily done in a few lines
+//      This effectively includes everything that isn't to do with page faults (virtual memory)
+
+cause_instr_addr_misaligned:
+    // cause a misaligned address trap
+    auipc x28, 0      // get current PC, which is aligned
+    addi x28, x28, 0x3  // add 1 to pc to create misaligned address
+    jr x28 // cause instruction address midaligned trap
+    ret
+
+cause_instr_access:
+    la x28, 0x0 // address zero is an address with no memory
+    sw x1, -4(sp) // push the return adress ontot the stack
+    addi sp, sp, -4
+    jalr x28 // cause instruction access trap
+    lw x1, 0(sp) // pop return adress back from the stack
+    addi sp, sp, 4
+    ret
+
+cause_illegal_instr:
+    .word 0x00000000 // a 32 bit zros is an illegal instruction
+    ret
+
+cause_breakpnt: // ****
+    ebreak
+    ret
+
+cause_load_addr_misaligned:
+    auipc x28, 0      // get current PC, which is aligned
+    addi x28, x28, 1
+    lw x29, 0(x28)    // load from a misaligned address
+    ret
+
+cause_load_acc:
+    la x28, 0         // 0 is an address with no memory
+    lw x29, 0(x28)    // load from unimplemented address
+    ret
+
+cause_store_addr_misaligned:
+    auipc x28, 0      // get current PC, which is aligned
+    addi x28, x28, 1
+    sw x29, 0(x28)     // store to a misaligned address
+    ret
+
+cause_store_acc: 
+    la x28, 0         // 0 is an address with no memory
+    sw x29, 0(x28)     // store to unimplemented address
+    ret
+
+cause_ecall:
+    // *** ASSUMES you have already gone to the mode you need to call this from.
+    ecall
+    ret
+
+cause_time_interrupt:
+    // The following code works for both RV32 and RV64.  
+    // RV64 alone would be easier using double-word adds and stores
+    li x28, 0x30          // Desired offset from the present time
+    la x29, 0x02004000    // MTIMECMP register in CLINT
+    la x30, 0x0200BFF8    // MTIME register in CLINT
+    lw x7, 0(x30)         // low word of MTIME
+    lw x31, 4(x30)         // high word of MTIME
+    add x28, x7, x28       // add desired offset to the current time
+    bgtu x28, x7, nowrap  // check new time exceeds current time (no wraparound)
+    addi x31, x31, 1       // if wrap, increment most significant word
+    sw x31,4(x29)          // store into most significant word of MTIMECMP
+nowrap:
+    sw x28, 0(x29)         // store into least significant word of MTIMECMP
+    loop: j loop         // wait until interrupt occurs
+    ret
+
+cause_soft_interrupt:
+    la x28, 0x02000000      // MSIP register in CLINT
+    li x29, 1               // 1 in the lsb
+    sw x29, 0(x28)          // Write MSIP bit
+    ret
+
+cause_ext_interrupt:
+    li x28, 0x10060000 // load base GPIO memory location
+    li x29, 0x1
+    sw x29, 8(x28) // enable the first pin as an output
+    sw x29, 28(x28) // set first pin to high interrupt enable
+    sw x29, 40(x28) // write a 1 to the first output pin (cause interrupt)
+    ret
+
+end_trap_triggers:
+.endm
+
+.macro TRAP_HANDLER MODE, VECTORED=1, DEBUG=0
+    // MODE decides which mode this trap handler will be taken in (M or S mode)
+    // Vectored decides whether interrumpts are handled with the vector table at trap_handler_MODE (1)
+    //      vs Using the non-vector approach the rest of the trap handler takes (0)
+    // DEBUG decides whether we will print mtval a string with status.mpie, status.mie, and status.mpp to the signature (1)
+    //      vs not saving that info to the signature (0)
+
+
+    //   Set up the exception Handler, keeping the original handler in x4.
+    la x1, trap_handler_\MODE\()
+    ori x1, x1, \VECTORED // set mode field of tvec to VECTORED, which will force vectored interrupts if it's 1.
+
+.if (\MODE\() == m)
+    csrrw x4, \MODE\()tvec, x1  // x4 reserved for "default" trap handler address that needs to be restored before halting this test.
+.else
+    csrw \MODE\()tvec, x1 // we only neet save the machine trap handler and this if statement ensures it isn't overwritten
+.endif
+
     li a0, 0
     li a1, 0 
     li a2, 0 // reset trap handler inputs to zero
 
-    // go to beginning of S file where we can decide between using the test data loop
-    // or using the macro inline code insertion
-    j s_file_begin
+    la x29, 0x02004000    // MTIMECMP register in CLINT
+    li x30, 0xFFFFFFFF
+    sw x30, 0(x29) // set mtimecmp to 0xFFFFFFFF to really make sure time interrupts don't go off immediately after being enabled
+
+    j trap_handler_end_\MODE\() // skip the trap handler when it is being defined.
 
 	// ---------------------------------------------------------------------------------------------
     // General traps Handler
@@ -96,38 +208,77 @@ RVTEST_CODE_BEGIN
     // --------------------------------------------------------------------------------------------
 
 
-machine_trap_handler:
+.align 2
+trap_handler_\MODE\():
+    j trap_unvectored_\MODE\() // for the unvectored implimentation: jump past this table of addresses into the actual handler
+    // *** ASSUMES that a cause value of 0 for an interrupt is unimplemented
+    // otherwise, a vectored interrupt handler should jump to trap_handler_\MODE\() + 4 * Interrupt cause code
+    // No matter the value of VECTORED, exceptions (not interrupts) are handled in an unvecotred way
+    j soft_interrupt_\MODE\()    // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table.
+    j segfault_\MODE\()            // 2: reserved
+    j soft_interrupt_\MODE\()    // 3: breakpoint
+    j segfault_\MODE\()            // 4: reserved
+    j time_interrupt_\MODE\()    // 5: load access fault
+    j segfault_\MODE\()            // 6: reserved
+    j time_interrupt_\MODE\()    // 7: store access fault
+    j segfault_\MODE\()            // 8: reserved
+    j ext_interrupt_\MODE\()     // 9: ecall from S-mode
+    j segfault_\MODE\()            // 10: reserved
+    j ext_interrupt_\MODE\()     // 11: ecall from M-mode
+    // 12 through >=16 are reserved or designated for platform use
+
+trap_unvectored_\MODE\():
     // The processor is always in machine mode when a trap takes us here
     // save registers on stack before using
     sw x1, -4(sp)       
     sw x5, -8(sp)      
 
     // Record trap
-    csrr x1, mcause     // record the mcause
+    csrr x1, \MODE\()cause     // record the mcause
     sw x1, 0(x16)        
     addi x6, x6, 4     
     addi x16, x16, 4    // update pointers for logging results
 
+.if (\DEBUG\() == 1) // record extra information (MTVAL, some status bits) about traps
+    csrr x1, \MODE\()tval
+    sw x1, 0(x16)
+    addi x6, x6, 4     
+    addi x16, x16, 4
+
+    csrr x1, \MODE\()status
+    .if (\MODE\() == m) // Taking traps in different modes means we want to get different bits from the status register.
+        li x5, 0x1888 // mask bits to select MPP, MPIE, and MIE.
+    .else
+        li x5, 0x122 // mask bits to select SPP, SPIE, and SIE.
+    .endif
+    and x5, x5, x1
+    sw x5, 0(x16) // store masked out status bits to the output
+    addi x6, x6, 4
+    addi x16, x16, 4
+
+.endif
+
     // Respond to trap based on cause
     // All interrupts should return after being logged
+    csrr x1, \MODE\()cause
     li x5, 0x8000000000000000   // if msb is set, it is an interrupt
     and x5, x5, x1
-    bnez x5, trapreturn   // return from interrupt
+    bnez x5, trapreturn_\MODE\()   // return from interrupt
     // Other trap handling is specified in the vector Table
     slli x1, x1, 2      // multiply cause by 4 to get offset in vector Table
-    la x5, trap_handler_vector_table
+    la x5, exception_vector_table_\MODE\()
     add x5, x5, x1      // compute address of vector in Table
     lw x5, 0(x5)        // fectch address of handler from vector Table
     jr x5               // and jump to the handler
     
-segfault:
+segfault_\MODE\():
     lw x5, -8(sp)      // restore registers from stack before faulting
     lw x1, -4(sp)       
     j terminate_test          // halt program.
 
-trapreturn:
+trapreturn_\MODE\():
     // look at the instruction to figure out whether to add 2 or 4 bytes to PC, or go to address specified in a1
-    csrr x1, mepc       // get the mepc
+    csrr x1, \MODE\()epc       // get the mepc
     addi x1, x1, 4 // *** should be 2 for compressed instructions, see note.
 
 
@@ -151,13 +302,13 @@ trapreturn:
 //     csrr x1, mepc       // get the mepc again    
 //     addi x1, x1, 4      // add 4 to find the next instruction
 
-trapreturn_specified:
+trapreturn_specified_\MODE\():
     // reset the necessary pointers and registers (x1, x5, x6, and the return address going to mepc)
     // so that when we return to a new virtual address, they're all in the right spot as well.
 
-    beqz a1, trapreturn_finished // either update values, of go to default return address.
+    beqz a1, trapreturn_finished_\MODE\() // either update values, of go to default return address.
 
-    la x5, trap_return_pagetype_table
+    la x5, trap_return_pagetype_table_\MODE\()
     slli a2, a2, 2
     add x5, x5, a2
     lw a2, 0(x5) // a2 = number of offset bits in current page type
@@ -189,54 +340,93 @@ trapreturn_specified:
     li a1, 0 
     li a2, 0 // reset trapreturn inputs to the trap handler
 
-trapreturn_finished:
-    csrw mepc, x1   // update the mepc with address of next instruction
+trapreturn_finished_\MODE\():
+    csrw \MODE\()epc, x1   // update the mepc with address of next instruction
     lw x5, -8(sp)   // restore registers from stack before returning
     lw x1, -4(sp)
-    mret  // return from trap
+    \MODE\()ret  // return from trap
 
-ecallhandler:
+ecallhandler_\MODE\():
     // Check input parameter a0. encoding above. 
     // *** ASSUMES: that this trap is being handled in machine mode. in other words, that nothing odd has been written to the medeleg or mideleg csrs.
     li x5, 2            // case 2: change to machine mode
-    beq a0, x5, ecallhandler_changetomachinemode
+    beq a0, x5, ecallhandler_changetomachinemode_\MODE\()
     li x5, 3            // case 3: change to supervisor mode
-    beq a0, x5, ecallhandler_changetosupervisormode
+    beq a0, x5, ecallhandler_changetosupervisormode_\MODE\()
     li x5, 4            // case 4: change to user mode
-    beq a0, x5, ecallhandler_changetousermode
+    beq a0, x5, ecallhandler_changetousermode_\MODE\()
     // unsupported ecalls should segfault
-    j segfault
+    j segfault_\MODE\()
 
-ecallhandler_changetomachinemode:
+ecallhandler_changetomachinemode_\MODE\():
     // Force mstatus.MPP (bits 12:11) to 11 to enter machine mode after mret
     li x1, 0b1100000000000
-    csrs mstatus, x1
-    j trapreturn        
+    csrs \MODE\()status, x1
+    j trapreturn_\MODE\()       
 
-ecallhandler_changetosupervisormode:
+ecallhandler_changetosupervisormode_\MODE\():
     // Force mstatus.MPP (bits 12:11) to 01 to enter supervisor mode after mret
     li x1, 0b1100000000000  
-    csrc mstatus, x1
+    csrc \MODE\()status, x1
     li x1, 0b0100000000000
-    csrs mstatus, x1
-    j trapreturn
+    csrs \MODE\()status, x1
+    j trapreturn_\MODE\()
 
-ecallhandler_changetousermode:
+ecallhandler_changetousermode_\MODE\():
     // Force mstatus.MPP (bits 12:11) to 00 to enter user mode after mret
     li x1, 0b1100000000000  
-    csrc mstatus, x1
-    j trapreturn
+    csrc \MODE\()status, x1
+    j trapreturn_\MODE\()
 
-instrfault:
+instrpagefault_\MODE\():
     lw x1, -4(sp) // load return address int x1 (the address AFTER the jal into faulting page)
-    j trapreturn_finished // puts x1 into mepc, restores stack and returns to program (outside of faulting page)
+    j trapreturn_finished_\MODE\() // puts x1 into mepc, restores stack and returns to program (outside of faulting page)
 
-illegalinstr:
-    j trapreturn // return to the code after recording the mcause
+instrfault_\MODE\():
+    lw x1, -4(sp) // load return address int x1 (the address AFTER the jal to the faulting address)
+    j trapreturn_finished_\MODE\() // return to the code after recording the mcause
 
-accessfault:
+illegalinstr_\MODE\():
+    j trapreturn_\MODE\() // return to the code after recording the mcause
+
+accessfault_\MODE\():
     // *** What do I have to do here?
-    j trapreturn
+    j trapreturn_\MODE\()
+
+addr_misaligned_\MODE\():
+    j trapreturn_\MODE\()
+
+breakpt_\MODE\():
+    j trapreturn_\MODE\()
+
+soft_interrupt_\MODE\():
+    li x5, 0x7EC // write 0x7EC (looks like VEC) to the output before the mcause and extras to indicate that this trap was handled with a vector table. 
+    sw x5, 0(x16)
+    addi x6, x6, 4
+    addi x16, x16, 4
+    la x28, 0x02000000 // Reset by clearing MSIP interrupt from CLINT
+    sw x0, 0(x28)
+    j trap_unvectored_\MODE\()
+
+time_interrupt_\MODE\():
+    li x5, 0x7EC
+    sw x5, 0(x16)
+    addi x6, x6, 4
+    addi x16, x16, 4
+    la x29, 0x02004000    // MTIMECMP register in CLINT
+    li x30, 0xFFFFFFFF
+    sw x30, 0(x29) // reset interrupt by setting mtimecmp to 0xFFFFFFFF
+    j trap_unvectored_\MODE\()
+
+ext_interrupt_\MODE\():
+    li x5, 0x7EC
+    sw x5, 0(x16)
+    addi x6, x6, 4
+    addi x16, x16, 4
+    li x28, 0x10060000 // reset interrupt by clearing all the GPIO bits
+    sw x0, 8(x28) // disable the first pin as an output
+    sw x0, 40(x28) // write a 0 to the first output pin (reset interrupt)
+    j trap_unvectored_\MODE\()
 
     // Table of trap behavior
     // lists what to do on each exception (not interrupts)
@@ -244,29 +434,30 @@ accessfault:
     // Expected exceptions should increment the EPC to the next instruction and return
 
     .align 2 // aligns this data table to an 4 byte boundary
-trap_handler_vector_table:
-    .4byte segfault      // 0: instruction address misaligned
-    .4byte instrfault    // 1: instruction access fault
-    .4byte illegalinstr  // 2: illegal instruction
-    .4byte segfault      // 3: breakpoint
-    .4byte segfault      // 4: load address misaligned
-    .4byte accessfault   // 5: load access fault
-    .4byte segfault      // 6: store address misaligned
-    .4byte accessfault   // 7: store access fault
-    .4byte ecallhandler  // 8: ecall from U-mode
-    .4byte ecallhandler  // 9: ecall from S-mode
-    .4byte segfault      // 10: reserved
-    .4byte ecallhandler  // 11: ecall from M-mode
-    .4byte instrfault    // 12: instruction page fault
-    .4byte trapreturn    // 13: load page fault
-    .4byte segfault      // 14: reserved
-    .4byte trapreturn    // 15: store page fault
+exception_vector_table_\MODE\():
+    .4byte addr_misaligned_\MODE\()      // 0: instruction address misaligned
+    .4byte instrfault_\MODE\()    // 1: instruction access fault
+    .4byte illegalinstr_\MODE\()  // 2: illegal instruction
+    .4byte breakpt_\MODE\()      // 3: breakpoint
+    .4byte addr_misaligned_\MODE\()      // 4: load address misaligned
+    .4byte accessfault_\MODE\()   // 5: load access fault
+    .4byte addr_misaligned_\MODE\()      // 6: store address misaligned
+    .4byte accessfault_\MODE\()   // 7: store access fault
+    .4byte ecallhandler_\MODE\()  // 8: ecall from U-mode
+    .4byte ecallhandler_\MODE\()  // 9: ecall from S-mode
+    .4byte segfault_\MODE\()      // 10: reserved
+    .4byte ecallhandler_\MODE\()  // 11: ecall from M-mode
+    .4byte instrpagefault_\MODE\()    // 12: instruction page fault
+    .4byte trapreturn_\MODE\()    // 13: load page fault
+    .4byte segfault_\MODE\()      // 14: reserved
+    .4byte trapreturn_\MODE\()    // 15: store page fault
 
 .align 2
-trap_return_pagetype_table:
+trap_return_pagetype_table_\MODE\():
     .4byte 0xC  // 0: kilopage has 12 offset bits
     .4byte 0x16 // 1: megapage has 22 offset bits
 
+trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler and continue with the test
 .endm
 
 // Test Summary table!
@@ -367,7 +558,7 @@ trap_return_pagetype_table:
 // they generally do not fault or cause issues as long as these modes are enabled 
 // *** add functionality to check if modes are enabled before jumping? maybe cause a fault if not?
 
-.macro GOTO_M_MODE RETURN_VPN RETURN_PAGETYPE
+.macro GOTO_M_MODE RETURN_VPN=0x0 RETURN_PAGETYPE=0x0
     li a0, 2 // determine trap handler behavior (go to machine mode)
     li a1, \RETURN_VPN // return VPN
     li a2, \RETURN_PAGETYPE // return page types
@@ -375,7 +566,7 @@ trap_return_pagetype_table:
     // now in S mode
 .endm
 
-.macro GOTO_S_MODE RETURN_VPN RETURN_PAGETYPE
+.macro GOTO_S_MODE RETURN_VPN=0x0 RETURN_PAGETYPE=0x0
     li a0, 3 // determine trap handler behavior (go to supervisor mode)
     li a1, \RETURN_VPN // return VPN
     li a2, \RETURN_PAGETYPE // return page types
@@ -383,7 +574,7 @@ trap_return_pagetype_table:
     // now in S mode
 .endm
 
-.macro GOTO_U_MODE RETURN_VPN RETURN_PAGETYPE
+.macro GOTO_U_MODE RETURN_VPN=0x0 RETURN_PAGETYPE=0x0
     li a0, 4 // determine trap handler behavior (go to user mode)
     li a1, \RETURN_VPN // return VPN
     li a2, \RETURN_PAGETYPE // return page types
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-minfo-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-minfo-01.S
index 9d1803a9..56bbe5b7 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-minfo-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-minfo-01.S
@@ -25,7 +25,7 @@
 
 INIT_TESTS
 
-s_file_begin:
+TRAP_HANDLER m
 
 // Test 5.2.3.1: testing Read-only access to Machine info CSRs 
 CSR_R_ACCESS mvendorid
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-misa-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-misa-01.S
index 6bbc3a82..e1476eaf 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-misa-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-misa-01.S
@@ -25,7 +25,7 @@
 
 INIT_TESTS
 
-s_file_begin:
+TRAP_HANDLER m
 // Test 5.3.2.2: Machine ISA register test
 
 // Misa is a specific case *** so I don't want to add a whole test case for reading nonzero but unkown value CSRs.
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mtvec-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mtvec-01.S
new file mode 100644
index 00000000..3930d227
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-mtvec-01.S
@@ -0,0 +1,45 @@
+///////////////////////////////////////////
+//
+// WALLY-unvectored-interrupt
+//
+// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
+//
+// Created 2022-03-11
+//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+#include "WALLY-TEST-LIB-64.h"
+
+INIT_TESTS
+
+// test 5.3.1.5 Unvectored interrupt tests 
+
+TRAP_HANDLER m, VECTORED=0, DEBUG=1 // turn off vectored interrupts, while turning on recording of mstatus bits.
+
+li x28, 0x8
+csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode
+WRITE_READ_CSR mie, 0xFFF // *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts
+
+// cause traps, ensuring that we DONT go through the vectored part of the trap handler
+// *** this assumes that interrupt code 0 remains reserved
+
+CAUSE_TIME_INTERRUPT // *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. 
+CAUSE_SOFT_INTERRUPT // *** exiting out of the trap handler after these is current;y broken
+CAUSE_EXT_INTERRUPT
+
+END_TESTS
+
+TEST_STACK_AND_DATA
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-scratch-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-scratch-01.S
index 4cb24cd1..3f8d5cc9 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-scratch-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-scratch-01.S
@@ -25,7 +25,8 @@
 
 INIT_TESTS
 
-s_file_begin:
+TRAP_HANDLER m
+
 // Test 5.3.2.3: Scratch registers test
 
 WRITE_READ_CSR mscratch, 0x111 // check that mscratch is readable and writeable in machine mode
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-sscratch-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-sscratch-s-01.S
index f42a61ef..761c639a 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-sscratch-s-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-sscratch-s-01.S
@@ -25,7 +25,7 @@
 
 INIT_TESTS
 
-s_file_begin:
+TRAP_HANDLER m
 
 // Test 5.3.2.3: Scratch registers test
 WRITE_READ_CSR sscratch, 0x111 // check that sscratch is readable and writeable in machine mode
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-stvec-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-stvec-01.S
new file mode 100644
index 00000000..688c7891
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-stvec-01.S
@@ -0,0 +1,55 @@
+///////////////////////////////////////////
+//
+// WALLY-unvectored-interrupt
+//
+// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
+//
+// Created 2022-03-11
+//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+#include "WALLY-TEST-LIB-64.h"
+
+INIT_TESTS
+
+// test 5.3.1.5 Unvectored interrupt tests 
+
+TRAP_HANDLER s, VECTORED=0, DEBUG=1 // turn off vectored interrupts, while turning on recording of mstatus bits.
+
+// li x28, 0x8
+// csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode
+// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts
+
+WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
+
+GOTO_S_MODE
+
+// cause traps, ensuring that we DONT go through the vectored part of the trap handler
+// *** this assumes that interrupt code 0 remains reserved
+
+// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. 
+// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
+// CAUSE_EXT_INTERRUPT
+
+GOTO_U_MODE 
+
+// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. 
+// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
+// CAUSE_EXT_INTERRUPT
+
+END_TESTS
+
+TEST_STACK_AND_DATA
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-01.S
new file mode 100644
index 00000000..45d34c34
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-01.S
@@ -0,0 +1,76 @@
+///////////////////////////////////////////
+//
+// WALLY-trap
+//
+// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
+//
+// Created 2022-02-20
+//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+#include "WALLY-TEST-LIB-64.h"
+
+INIT_TESTS
+
+CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
+
+TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps
+
+li x28, 0x8
+csrs mstatus, x28 // set mstatus.MIE bit to 1
+WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources // *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts
+
+// test 5.3.1.4 Basic trap tests 
+
+// jal cause_instr_addr_misaligned //skipped becuase this exception may be impossible when compressed instructions are enabled)
+jal cause_instr_access
+jal cause_illegal_instr
+jal cause_breakpnt
+jal cause_load_addr_misaligned
+jal cause_load_acc
+jal cause_store_addr_misaligned
+jal cause_store_acc
+GOTO_U_MODE // Causes M mode ecall
+GOTO_S_MODE // Causes U mode ecall
+GOTO_M_MODE // Causes S mode ecall
+
+jal cause_time_interrupt // *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. 
+jal cause_soft_interrupt // *** exiting out of the trap handler after these is current;y broken
+jal cause_ext_interrupt
+
+// try the traps again with mideleg = medeleg = all 1's to ensure traps still go to M mode from M mode
+
+WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF
+WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
+
+// jal cause_instr_addr_misaligned //skipped becuase this exception may be impossible when compressed instructions are enabled)
+jal cause_instr_access
+jal cause_illegal_instr
+jal cause_breakpnt
+jal cause_load_addr_misaligned
+jal cause_load_acc
+jal cause_store_addr_misaligned
+jal cause_store_acc
+jal cause_ecall // M mode ecall
+
+jal cause_time_interrupt // *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. 
+jal cause_soft_interrupt // *** exiting out of the trap handler after these is current;y broken
+jal cause_ext_interrupt
+
+END_TESTS
+
+TEST_STACK_AND_DATA
+
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S
new file mode 100644
index 00000000..9a813d9a
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S
@@ -0,0 +1,85 @@
+///////////////////////////////////////////
+//
+// WALLY-trap-s
+//
+// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
+//
+// Created 2022-03-11
+//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+#include "WALLY-TEST-LIB-64.h"
+
+INIT_TESTS
+
+// test 5.3.1.4 Basic trap tests 
+
+TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps
+TRAP_HANDLER s, DEBUG=1 // have S mode trap handler as well
+
+// Like WALLY-trap, cause all the same traps from S mode and make sure they go to machine mode with zeroed mideleg, medeleg
+
+GOTO_S_MODE
+
+li x28, 0x8
+csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode
+// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts
+
+
+// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled)
+CAUSE_INSTR_ACCESS
+CAUSE_ILLEGAL_INSTR
+CAUSE_BREAKPNT
+CAUSE_LOAD_ADDR_MISALIGNED
+CAUSE_LOAD_ACC
+CAUSE_STORE_ADDR_MISALIGNED
+CAUSE_STORE_ACC
+CAUSE_ECALL
+
+// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. 
+// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
+// CAUSE_EXT_INTERRUPT
+
+
+// Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler
+// We can tell which one becuase the different trap handler modes write different bits of the status register 
+// to the output when debug is on.
+
+GOTO_M_MODE // so we can write the delegate registers
+
+WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF
+WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
+
+GOTO_S_MODE
+
+// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled)
+CAUSE_INSTR_ACCESS
+CAUSE_ILLEGAL_INSTR
+CAUSE_BREAKPNT
+CAUSE_LOAD_ADDR_MISALIGNED
+CAUSE_LOAD_ACC
+CAUSE_STORE_ADDR_MISALIGNED
+CAUSE_STORE_ACC
+CAUSE_ECALL
+
+// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. 
+// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
+// CAUSE_EXT_INTERRUPT
+
+END_TESTS
+
+TEST_STACK_AND_DATA
+
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S
new file mode 100644
index 00000000..498c2ee3
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-u-01.S
@@ -0,0 +1,84 @@
+///////////////////////////////////////////
+//
+// WALLY-trap-u
+//
+// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
+//
+// Created 2022-03-11
+//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+#include "WALLY-TEST-LIB-64.h"
+
+INIT_TESTS
+
+// test 5.3.1.4 Basic trap tests 
+
+TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps
+TRAP_HANDLER s, DEBUG=1 // have S mode trap handler as well
+
+// Like WALLY-trap, cause all the same traps from U mode and make sure they go to machine mode with zeroed mideleg, medeleg
+
+GOTO_U_MODE
+
+// li x28, 0x8
+// csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode
+// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts
+
+
+// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled)
+CAUSE_INSTR_ACCESS
+CAUSE_ILLEGAL_INSTR
+CAUSE_BREAKPNT
+CAUSE_LOAD_ADDR_MISALIGNED
+CAUSE_LOAD_ACC
+CAUSE_STORE_ADDR_MISALIGNED
+CAUSE_STORE_ACC
+CAUSE_ECALL
+
+// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. 
+// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
+// CAUSE_EXT_INTERRUPT
+
+
+// Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler
+// We can tell which one becuase the different trap handler modes write different bits of the status register 
+// to the output when debug is on.
+
+GOTO_M_MODE // so we can write the delegate registers
+
+WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF
+WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
+
+GOTO_U_MODE
+
+// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled)
+CAUSE_INSTR_ACCESS
+CAUSE_ILLEGAL_INSTR
+CAUSE_BREAKPNT
+CAUSE_LOAD_ADDR_MISALIGNED
+CAUSE_LOAD_ACC
+CAUSE_STORE_ADDR_MISALIGNED
+CAUSE_STORE_ACC
+CAUSE_ECALL
+
+// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. 
+// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
+// CAUSE_EXT_INTERRUPT
+
+END_TESTS
+
+TEST_STACK_AND_DATA
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h
index 534fd433..ed16247d 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h
@@ -117,7 +117,7 @@ cause_ecall:
 cause_time_interrupt:
     // The following code works for both RV32 and RV64.  
     // RV64 alone would be easier using double-word adds and stores
-    li x28, 0x100          // Desired offset from the present time
+    li x28, 0x30          // Desired offset from the present time
     la x29, 0x02004000    // MTIMECMP register in CLINT
     la x30, 0x0200BFF8    // MTIME register in CLINT
     lw x7, 0(x30)         // low word of MTIME
@@ -158,9 +158,7 @@ end_trap_triggers:
 
     //   Set up the exception Handler, keeping the original handler in x4.
     la x1, trap_handler_\MODE\()
-.if (\VECTORED\() == 1)
-    ori x1, x1, 0x1 // set mode field of tvec to 1, forcing vectored interrupts
-.endif
+    ori x1, x1, \VECTORED // set mode field of tvec to VECTORED, which will force vectored interrupts if it's 1.
 
 .if (\MODE\() == m)
     csrrw x4, \MODE\()tvec, x1  // x4 reserved for "default" trap handler address that needs to be restored before halting this test.
@@ -172,6 +170,10 @@ end_trap_triggers:
     li a1, 0 
     li a2, 0 // reset trap handler inputs to zero
 
+    la x29, 0x02004000    // MTIMECMP register in CLINT
+    li x30, 0xFFFFFFFF
+    sd x30, 0(x29) // set mtimecmp to 0xFFFFFFFF to really make sure time interrupts don't go off immediately after being enabled
+
     j trap_handler_end_\MODE\() // skip the trap handler when it is being defined.
 
 	// ---------------------------------------------------------------------------------------------
@@ -214,17 +216,17 @@ trap_handler_\MODE\():
     // *** ASSUMES that a cause value of 0 for an interrupt is unimplemented
     // otherwise, a vectored interrupt handler should jump to trap_handler_\MODE\() + 4 * Interrupt cause code
     // No matter the value of VECTORED, exceptions (not interrupts) are handled in an unvecotred way
-    j s_soft_interrupt_\MODE\()    // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table.
+    j soft_interrupt_\MODE\()    // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table.
     j segfault_\MODE\()            // 2: reserved
-    j m_soft_interrupt_\MODE\()    // 3: breakpoint
+    j soft_interrupt_\MODE\()    // 3: breakpoint
     j segfault_\MODE\()            // 4: reserved
-    j s_time_interrupt_\MODE\()    // 5: load access fault
+    j time_interrupt_\MODE\()    // 5: load access fault
     j segfault_\MODE\()            // 6: reserved
-    j m_time_interrupt_\MODE\()    // 7: store access fault
+    j time_interrupt_\MODE\()    // 7: store access fault
     j segfault_\MODE\()            // 8: reserved
-    j s_ext_interrupt_\MODE\()     // 9: ecall from S-mode
+    j ext_interrupt_\MODE\()     // 9: ecall from S-mode
     j segfault_\MODE\()            // 10: reserved
-    j m_ext_interrupt_\MODE\()     // 11: ecall from M-mode
+    j ext_interrupt_\MODE\()     // 11: ecall from M-mode
     // 12 through >=16 are reserved or designated for platform use
 
 trap_unvectored_\MODE\():
@@ -245,12 +247,11 @@ trap_unvectored_\MODE\():
     addi x16, x16, 8
 
     csrr x1, \MODE\()status
-.if (\MODE\() == m) // Taking traps in different modes means we want to get different bits from the status register.
-    li x5, 0x1888 // mask bits to select MPP, MPIE, and MIE.
-.else
-    li x5, 0x122 // mask bits to select SPP, SPIE, and SIE.
-.endif
-
+    .if (\MODE\() == m) // Taking traps in different modes means we want to get different bits from the status register.
+        li x5, 0x1888 // mask bits to select MPP, MPIE, and MIE.
+    .else
+        li x5, 0x122 // mask bits to select SPP, SPIE, and SIE.
+    .endif
     and x5, x5, x1
     sd x5, 0(x16) // store masked out status bits to the output
     addi x6, x6, 8
@@ -265,7 +266,6 @@ trap_unvectored_\MODE\():
     and x5, x5, x1
     bnez x5, trapreturn_\MODE\()   // return from interrupt
     // Other trap handling is specified in the vector Table
-    csrr x1, \MODE\()cause
     slli x1, x1, 3      // multiply cause by 8 to get offset in vector Table
     la x5, exception_vector_table_\MODE\()
     add x5, x5, x1      // compute address of vector in Table
@@ -345,7 +345,7 @@ trapreturn_finished_\MODE\():
     csrw \MODE\()epc, x1       // update the epc with address of next instruction
     ld x5, -16(sp)      // restore registers from stack before returning
     ld x1, -8(sp)
-    csrw \MODE\()ip, 0x0 // clear interrupt pending register to indicate interrupt has been handled
+    // *** this should be handled by indirectly clearing this bit csrw \MODE\()ip, 0x0 // clear interrupt pending register to indicate interrupt has been handled
     \MODE\()ret  // return from trap
 
 ecallhandler_\MODE\():
@@ -376,7 +376,7 @@ ecallhandler_changetosupervisormode_\MODE\():
 ecallhandler_changetousermode_\MODE\():
     // Force mstatus.MPP (bits 12:11) to 00 to enter user mode after mret
     li x1, 0b1100000000000  
-    csrc mstatus, x1
+    csrc \MODE\()status, x1
     j trapreturn_\MODE\()
 
 instrpagefault_\MODE\():
@@ -400,7 +400,7 @@ addr_misaligned_\MODE\():
 breakpt_\MODE\():
     j trapreturn_\MODE\()
 
-s_soft_interrupt_\MODE\(): // these labels are here to make sure the code compiles, but don't actually do anything yet
+soft_interrupt_\MODE\():
     li x5, 0x7EC // write 0x7EC (looks like VEC) to the output before the mcause and extras to indicate that this trap was handled with a vector table. 
     sd x5, 0(x16)
     addi x6, x6, 8
@@ -409,30 +409,19 @@ s_soft_interrupt_\MODE\(): // these labels are here to make sure the code compil
     sw x0, 0(x28)
     j trap_unvectored_\MODE\()
 
-m_soft_interrupt_\MODE\():
+time_interrupt_\MODE\():
     li x5, 0x7EC
     sd x5, 0(x16)
     addi x6, x6, 8
     addi x16, x16, 8
-    la x28, 0x02000000 // Reset by clearing MSIP interrupt from CLINT
-    sw x0, 0(x28)
+
+    la x29, 0x02004000    // MTIMECMP register in CLINT
+    li x30, 0xFFFFFFFF
+    sd x30, 0(x29) // reset interrupt by setting mtimecmp to 0xFFFFFFFF
+
     j trap_unvectored_\MODE\()
 
-s_time_interrupt_\MODE\():
-    li x5, 0x7EC
-    sd x5, 0(x16)
-    addi x6, x6, 8
-    addi x16, x16, 8
-    j trap_unvectored_\MODE\()
-
-m_time_interrupt_\MODE\():
-    li x5, 0x7EC
-    sd x5, 0(x16)
-    addi x6, x6, 8
-    addi x16, x16, 8
-    j trap_unvectored_\MODE\()
-
-s_ext_interrupt_\MODE\():
+ext_interrupt_\MODE\():
     li x5, 0x7EC
     sd x5, 0(x16)
     addi x6, x6, 8
@@ -442,17 +431,6 @@ s_ext_interrupt_\MODE\():
     sw x0, 40(x28) // write a 0 to the first output pin (reset interrupt)
     j trap_unvectored_\MODE\()
 
-m_ext_interrupt_\MODE\():
-    li x5, 0x7EC
-    sd x5, 0(x16)
-    addi x6, x6, 8
-    addi x16, x16, 8
-    li x28, 0x10060000 // reset interrupt by clearing all the GPIO bits
-    sw x0, 8(x28) // disable the first pin as an output
-    sw x0, 40(x28) // write a 0 to the first output pin (reset interrupt)
-    j trap_unvectored_\MODE\()
-
-
     // Table of trap behavior
     // lists what to do on each exception (not interrupts)
     // unexpected exceptions should cause segfaults for easy detection
@@ -720,87 +698,6 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a
     addi x16, x16, 8 
 .endm
 
-// // The following tests involve causing many of the interrupts and exceptions that are easily done in a few lines
-// //      This effectively includes everything that isn't to do with page faults (virtual memory)
-
-// .macro CAUSE_INSTR_ADDR_MISALIGNED
-//     // cause a misaligned address trap
-//     auipc x28, 0      // get current PC, which is aligned
-//     addi x28, x28, 0x1  // add 1 to pc to create misaligned address
-//     jalr x28 // cause instruction address midaligned trap
-// .endm
-
-// .macro CAUSE_INSTR_ACCESS
-//     la x28, 0x0 // address zero is an address with no memory
-//     jalr x28 // cause instruction access trap
-// .endm
-
-// .macro CAUSE_ILLEGAL_INSTR
-//     .word 0x00000000 // a 32 bit zros is an illegal instruction
-// .endm
-
-// .macro CAUSE_BREAKPNT // ****
-//     ebreak
-// .endm
-
-// .macro CAUSE_LOAD_ADDR_MISALIGNED
-//     auipc x28, 0      // get current PC, which is aligned
-//     addi x28, x28, 1
-//     lw x29, 0(x28)    // load from a misaligned address
-// .endm
-
-// .macro CAUSE_LOAD_ACC
-//     la x28, 0         // 0 is an address with no memory
-//     lw x29, 0(x28)    // load from unimplemented address
-// .endm
-
-// .macro CAUSE_STORE_ADDR_MISALIGNED
-//     auipc x28, 0      // get current PC, which is aligned
-//     addi x28, x28, 1
-//     sw x29, 0(x28)     // store to a misaligned address
-// .endm
-
-// .macro CAUSE_STORE_ACC 
-//     la x28, 0         // 0 is an address with no memory
-//     sw x29, 0(x28)     // store to unimplemented address
-// .endm
-
-// .macro CAUSE_ECALL
-//     // *** ASSUMES you have already gone to the mode you need to call this from.
-//     ecall
-// .endm
-
-// .macro CAUSE_TIME_INTERRUPT
-//     // The following code works for both RV32 and RV64.  
-//     // RV64 alone would be easier using double-word adds and stores
-//     li x28, 0x100          // Desired offset from the present time
-//     la x29, 0x02004000    // MTIMECMP register in CLINT
-//     la x30, 0x0200BFF8    // MTIME register in CLINT
-//     lw x7, 0(x30)         // low word of MTIME
-//     lw x31, 4(x30)         // high word of MTIME
-//     add x28, x7, x28       // add desired offset to the current time
-//     bgtu x28, x7, nowrap  // check new time exceeds current time (no wraparound)
-//     addi x31, x31, 1       // if wrap, increment most significant word
-//     sw x31,4(x29)          // store into most significant word of MTIMECMP
-// nowrap:
-//     sw x28, 0(x29)         // store into least significant word of MTIMECMP
-//     loop: j loop         // wait until interrupt occurs
-// .endm
-
-// .macro CAUSE_SOFT_INTERRUPT
-//     la x28, 0x02000000      // MSIP register in CLINT
-//     li x29, 1               // 1 in the lsb
-//     sw x29, 0(x28)          // Write MSIP bit
-// .endm
-
-// .macro CAUSE_EXT_INTERRUPT
-//     li x28, 0x10060000 // load base GPIO memory location
-//     li x29, 0x1
-//     sw x29, 8(x28) // enable the first pin as an output
-//     sw x29, 28(x28) // set first pin to high interrupt enable
-//     sw x29, 40(x28) // write a 1 to the first output pin (cause interrupt)
-// .endm
-
 .macro END_TESTS
     // invokes one final ecall to return to machine mode then terminates this program, so the output is
     //      0x8: termination called from U mode