diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index 4da66893..935d6b01 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -44,8 +44,7 @@ module fpu ( output logic FpLoadStoreM, // Fp load instruction? (to LSU) output logic FStallD, // Stall the decode stage (To HZU) output logic FWriteIntE, // integer register write enable (to IEU) - output logic [`XLEN-1:0] FWriteDataE, // Data to be written to memory (to IEU) - only used if `XLEN >`FLEN *** delete this - output logic [`FLEN-1:0] FWriteDataM, // Data to be written to memory (to IEU) - only used if `XLEN <`FLEN + output logic [`FLEN-1:0] FWriteDataM, // Data to be written to memory (to LSU) output logic [`XLEN-1:0] FIntResM, // data to be written to integer register (to IEU) output logic [`XLEN-1:0] FCvtIntResW, // convert result to to be written to integer register (to IEU) output logic [1:0] FResSelW, // final result selection (to IEU) @@ -59,6 +58,9 @@ module fpu ( // - if there are any unsused bits the most significant bits are filled with 1s // single stored in a double: | 32 1s | single precision value | // - sets the underflow after rounding + + // LSU interface + logic [`FLEN-1:0] FWriteDataE; // control signals logic FRegWriteW; // FP register write enable @@ -289,18 +291,17 @@ module fpu ( // - FP uses NaN-blocking format // - if there are any unsused bits the most significant bits are filled with 1s - logic [`FLEN-1:0] WriteDataE; - if(`FPSIZES == 1) assign WriteDataE = YE; - else if(`FPSIZES == 2) assign WriteDataE = FmtE ? YE : {`FLEN/`LEN1{YE[`LEN1-1:0]}}; + if(`FPSIZES == 1) assign FWriteDataE = YE; + else if(`FPSIZES == 2) assign FWriteDataE = FmtE ? YE : {`FLEN/`LEN1{YE[`LEN1-1:0]}}; else always_comb case(FmtE) - `Q_FMT: WriteDataE = YE; - `D_FMT: WriteDataE = {`FLEN/`D_LEN{YE[`D_LEN-1:0]}}; - `S_FMT: WriteDataE = {`FLEN/`S_LEN{YE[`S_LEN-1:0]}}; - `H_FMT: WriteDataE = {`FLEN/`H_LEN{YE[`H_LEN-1:0]}}; + `Q_FMT: FWriteDataE = YE; + `D_FMT: FWriteDataE = {`FLEN/`D_LEN{YE[`D_LEN-1:0]}}; + `S_FMT: FWriteDataE = {`FLEN/`S_LEN{YE[`S_LEN-1:0]}}; + `H_FMT: FWriteDataE = {`FLEN/`H_LEN{YE[`H_LEN-1:0]}}; endcase - flopenrc #(`FLEN) EMWriteDataReg (clk, reset, FlushM, ~StallM, WriteDataE, FWriteDataM); + flopenrc #(`FLEN) FWriteDataMReg (clk, reset, FlushM, ~StallM, FWriteDataE, FWriteDataM); // NaN Block SrcA generate diff --git a/pipelined/src/ieu/datapath.sv b/pipelined/src/ieu/datapath.sv index 71558178..73e9e94e 100644 --- a/pipelined/src/ieu/datapath.sv +++ b/pipelined/src/ieu/datapath.sv @@ -45,7 +45,6 @@ module datapath ( input logic JumpE, input logic BranchSignedE, input logic IllegalFPUInstrE, - input logic [`XLEN-1:0] FWriteDataE, input logic [`XLEN-1:0] PCE, input logic [`XLEN-1:0] PCLinkE, output logic [1:0] FlagsE, @@ -56,7 +55,7 @@ module datapath ( input logic FWriteIntM, input logic [`XLEN-1:0] FIntResM, output logic [`XLEN-1:0] SrcAM, - output logic [`XLEN-1:0] WriteDataE, + output logic [`XLEN-1:0] WriteDataM, // Writeback stage signals input logic StallW, FlushW, (* mark_debug = "true" *) input logic RegWriteW, @@ -118,6 +117,7 @@ module datapath ( flopenrc #(`XLEN) SrcAMReg(clk, reset, FlushM, ~StallM, SrcAE, SrcAM); flopenrc #(`XLEN) IEUResultMReg(clk, reset, FlushM, ~StallM, IEUResultE, IEUResultM); flopenrc #(5) RdMReg(clk, reset, FlushM, ~StallM, RdE, RdM); + flopenrc #(`XLEN) WriteDataMReg(clk, reset, FlushM, ~StallM, ForwardedSrcBE, WriteDataM); // Writeback stage pipeline register and logic flopenrc #(`XLEN) IFResultWReg(clk, reset, FlushW, ~StallW, IFResultM, IFResultW); @@ -133,7 +133,6 @@ module datapath ( assign IFResultM = IEUResultM; mux5 #(`XLEN) resultmuxW(IFResultW, ReadDataW, CSRReadValW, MDUResultW, SCResultW, ResultSrcW, ResultW); end - assign WriteDataE = ForwardedSrcBE; // handle Store Conditional result if atomic extension supported if (`A_SUPPORTED) assign SCResultW = {{(`XLEN-1){1'b0}}, SquashSCW}; diff --git a/pipelined/src/ieu/ieu.sv b/pipelined/src/ieu/ieu.sv index b47cd1d2..52080706 100644 --- a/pipelined/src/ieu/ieu.sv +++ b/pipelined/src/ieu/ieu.sv @@ -41,7 +41,6 @@ module ieu ( input logic [`XLEN-1:0] PCLinkE, input logic FWriteIntE, input logic IllegalFPUInstrE, - input logic [`XLEN-1:0] FWriteDataE, output logic [`XLEN-1:0] IEUAdrE, output logic MDUE, W64E, output logic [2:0] Funct3E, @@ -51,7 +50,7 @@ module ieu ( input logic SquashSCW, // from LSU output logic [1:0] MemRWM, // read/write control goes to LSU output logic [1:0] AtomicM, // atomic control goes to LSU - output logic [`XLEN-1:0] WriteDataE, // Address and write data to LSU + output logic [`XLEN-1:0] WriteDataM, // write data to LSU output logic [2:0] Funct3M, // size and signedness to LSU output logic [`XLEN-1:0] SrcAM, // to privilege and fpu @@ -107,8 +106,8 @@ module ieu ( datapath dp( .clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE, .ALUControlE, .Funct3E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .JumpE, .BranchSignedE, .IllegalFPUInstrE, - .FWriteDataE, .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, - .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataE, .FResSelW, + .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, + .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FResSelW, .StallW, .FlushW, .RegWriteW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW, .CSRReadValW, .MDUResultW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW); diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 7b4284fa..121e3082 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -50,7 +50,7 @@ module lsu ( // address and write data input logic [`XLEN-1:0] IEUAdrE, (* mark_debug = "true" *)output logic [`XLEN-1:0] IEUAdrM, - input logic [`XLEN-1:0] WriteDataE, + (* mark_debug = "true" *)input logic [`XLEN-1:0] WriteDataM, output logic [`LLEN-1:0] ReadDataW, // cpu privilege input logic [1:0] PrivilegeModeW, @@ -111,14 +111,12 @@ module lsu ( logic SelLSUBusWord; logic DataDAPageFaultM; logic [`XLEN-1:0] LSUWriteDataM; - logic [`XLEN-1:0] WriteDataM; logic [`LLEN-1:0] ReadDataM; logic [(`LLEN-1)/8:0] ByteMaskM, FinalByteMaskM; // *** TO DO: Burst mode flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM); - flopenrc #(`XLEN) WriteDataMReg(clk, reset, FlushM, ~StallM, WriteDataE, WriteDataM); // *** move this flop to IEU assign IEUAdrExtM = {2'b00, IEUAdrM}; assign LSUStallM = DCacheStallM | InterlockStall | BusStall;