forked from Github_Repos/cvw
This icpred and btb changes are causing a performance issue.
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@ -174,9 +174,9 @@ module bpred (
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// this will result in PCD not being equal to the fall through address PCLinkE (PCE+4).
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// this will result in PCD not being equal to the fall through address PCLinkE (PCE+4).
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// The next instruction is always valid as no other flush would occur at the same time as the branch and not
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// The next instruction is always valid as no other flush would occur at the same time as the branch and not
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// also flush the branch. This will change in a superscaler cpu.
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// also flush the branch. This will change in a superscaler cpu.
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assign BPPCWrongE = PCCorrectE != PCD;
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assign BPPCWrongE = ;
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// branch is wrong only if the PC does not match and both the Decode and Fetch stages have valid instructions.
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// branch is wrong only if the PC does not match and both the Decode and Fetch stages have valid instructions.
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assign BPWrongE = BPPCWrongE & InstrValidE & InstrValidD;
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assign BPWrongE = (PCCorrectE != PCD) & InstrValidE & InstrValidD;
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flopenrc #(1) BPPredWrongMReg(clk, reset, FlushM, ~StallM, BPWrongE, BPPredWrongM);
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flopenrc #(1) BPPredWrongMReg(clk, reset, FlushM, ~StallM, BPWrongE, BPPredWrongM);
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// Output the predicted PC or corrected PC on miss-predict.
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// Output the predicted PC or corrected PC on miss-predict.
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