From 3261f31e88236619ef21fffed61f3b95bf31977a Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 27 Feb 2023 20:00:50 -0600 Subject: [PATCH] This icpred and btb changes are causing a performance issue. --- src/ifu/bpred/bpred.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index 3ad0506c..5c8938bc 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -174,9 +174,9 @@ module bpred ( // this will result in PCD not being equal to the fall through address PCLinkE (PCE+4). // The next instruction is always valid as no other flush would occur at the same time as the branch and not // also flush the branch. This will change in a superscaler cpu. - assign BPPCWrongE = PCCorrectE != PCD; + assign BPPCWrongE = ; // branch is wrong only if the PC does not match and both the Decode and Fetch stages have valid instructions. - assign BPWrongE = BPPCWrongE & InstrValidE & InstrValidD; + assign BPWrongE = (PCCorrectE != PCD) & InstrValidE & InstrValidD; flopenrc #(1) BPPredWrongMReg(clk, reset, FlushM, ~StallM, BPWrongE, BPPredWrongM); // Output the predicted PC or corrected PC on miss-predict.