diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 75c1acc1..07194535 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -82,7 +82,6 @@ module lsu ( ); logic [`PA_BITS-1:0] LSUPAdrM; // from mmu to dcache - logic [`XLEN+1:0] IEUAdrExtM; logic DTLBMissM; logic DTLBWriteM; logic [1:0] LSURWM; @@ -107,54 +106,27 @@ module lsu ( //////////////////////////////////////////////////////////////////////////////////////////////// flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM); - assign IEUAdrExtM = {2'b00, IEUAdrM}; + logic [`XLEN+1:0] IEUAdrExtM; + assign IEUAdrExtM = {2'b00, IEUAdrM}; + if(`MEM_VIRTMEM) begin : MEM_VIRTMEM - // *** encapsulate as lsuvirtmem - logic AnyCPUReqM; - logic [`PA_BITS-1:0] HPTWAdr; - logic HPTWRead; - logic [2:0] HPTWSize; - logic SelReplayCPURequest; + lsuvirtmem lsuvirtmem(.clk, .reset, .StallW, .MemRWM, .AtomicM, .ITLBMissF, .ITLBWriteF, + .DTLBMissM, .DTLBWriteM, .TrapM, .DCacheStallM, .SATP_REGW, .PCF, + .ReadDataM, .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M, .IEUAdrM, + .IEUAdrExtM, .PTE, .PageType, .PreLSURWM, .LSUAtomicM, .IEUAdrE, + .LSUAdrE, .PreLSUPAdrM, .CPUBusy, .InterlockStall, .SelHPTW, + .IgnoreRequest); - assign AnyCPUReqM = (|MemRWM) | (|AtomicM); - - interlockfsm interlockfsm (.clk, .reset, .AnyCPUReqM, .ITLBMissF, .ITLBWriteF, - .DTLBMissM, .DTLBWriteM, .TrapM, .DCacheStallM, - .InterlockStall, .SelReplayCPURequest, .SelHPTW, - .IgnoreRequest); - - hptw hptw(.clk, .reset, .SATP_REGW, .PCF, .IEUAdrM, - .ITLBMissF(ITLBMissF & ~TrapM), - .DTLBMissM(DTLBMissM & ~TrapM), - .PTE, .PageType, .ITLBWriteF, .DTLBWriteM, - .HPTWReadPTE(ReadDataM), - .DCacheStallM, .HPTWAdr, .HPTWRead, .HPTWSize); - - // arbiter between IEU and hptw - - // multiplex the outputs to LSU - mux2 #(2) rwmux(MemRWM, {HPTWRead, 1'b0}, SelHPTW, PreLSURWM); - mux2 #(3) sizemux(Funct3M, HPTWSize, SelHPTW, LSUFunct3M); - mux2 #(7) funct7mux(Funct7M, 7'b0, SelHPTW, LSUFunct7M); - mux2 #(2) atomicmux(AtomicM, 2'b00, SelHPTW, LSUAtomicM); - mux2 #(12) adremux(IEUAdrE[11:0], HPTWAdr[11:0], SelHPTW, PreLSUAdrE); - mux2 #(12) replaymux(PreLSUAdrE, IEUAdrM[11:0], SelReplayCPURequest, LSUAdrE); // replay cpu request after hptw. - mux2 #(`PA_BITS) lsupadrmux(IEUAdrExtM[`PA_BITS-1:0], HPTWAdr, SelHPTW, PreLSUPAdrM); - - // always block interrupts when using the hardware page table walker. - assign CPUBusy = StallW & ~SelHPTW; - end // if (`MEM_VIRTMEM) else begin assign {InterlockStall, SelHPTW, PTE, PageType, DTLBWriteM, ITLBWriteF} = '0; assign IgnoreRequest = TrapM; assign CPUBusy = StallW; assign LSUAdrE = PreLSUAdrE; assign LSUFunct3M = Funct3M; assign LSUFunct7M = Funct7M; assign LSUAtomicM = AtomicM; - assign PreLSURWM = MemRWM; assign PreLSUAdrE = IEUAdrE[11:0]; assign PreLSUPAdrM = IEUAdrExtM; + assign PreLSURWM = MemRWM; assign PreLSUAdrE = IEUAdrE[11:0]; assign PreLSUPAdrM = IEUAdrExtM[`PA_BITS-1:0]; end - // **** look into this confusing signal. // This signal is confusing. CommittedM tells the CPU's trap unit the current instruction // in the memory stage is a memory operaton and that memory operation is either completed diff --git a/pipelined/src/lsu/lsuvirtmen.sv b/pipelined/src/lsu/lsuvirtmen.sv new file mode 100644 index 00000000..60e76f7f --- /dev/null +++ b/pipelined/src/lsu/lsuvirtmen.sv @@ -0,0 +1,102 @@ +/////////////////////////////////////////// +// lsuvirtmem.sv +// +// Written: Ross Thompson ross1728@gmail.com January 30, 2022 +// Modified: +// +// Purpose: Encapsulates the hptw and muxes required to support virtual memory. +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module lsuvirtmem( + input logic clk, reset, StallW, + input logic [1:0] MemRWM, + input logic [1:0] AtomicM, + input logic ITLBMissF, + output logic ITLBWriteF, + input logic DTLBMissM, + output logic DTLBWriteM, + input logic TrapM, + input logic DCacheStallM, + input logic [`XLEN-1:0] SATP_REGW, // from csr + input logic [`XLEN-1:0] PCF, + input logic [`XLEN-1:0] ReadDataM, + input logic [2:0] Funct3M, + output logic [2:0] LSUFunct3M, + input logic [6:0] Funct7M, + output logic [6:0] LSUFunct7M, + input logic [`XLEN-1:0] IEUAdrE, + input logic [`XLEN-1:0] IEUAdrM, + output logic [`XLEN-1:0] PTE, + output logic [1:0] PageType, + output logic [1:0] PreLSURWM, + output logic [1:0] LSUAtomicM, + output logic [11:0] LSUAdrE, + output logic [`PA_BITS-1:0] PreLSUPAdrM, + input logic [`XLEN+1:0] IEUAdrExtM, + + output logic InterlockStall, + output logic CPUBusy, + output logic SelHPTW, + output logic IgnoreRequest); + + + logic AnyCPUReqM; + logic [`PA_BITS-1:0] HPTWAdr; + logic HPTWRead; + logic [2:0] HPTWSize; + logic SelReplayCPURequest; + logic [11:0] PreLSUAdrE; + + + + assign AnyCPUReqM = (|MemRWM) | (|AtomicM); + + interlockfsm interlockfsm (.clk, .reset, .AnyCPUReqM, .ITLBMissF, .ITLBWriteF, + .DTLBMissM, .DTLBWriteM, .TrapM, .DCacheStallM, + .InterlockStall, .SelReplayCPURequest, .SelHPTW, + .IgnoreRequest); + + hptw hptw(.clk, .reset, .SATP_REGW, .PCF, .IEUAdrM, + .ITLBMissF(ITLBMissF & ~TrapM), + .DTLBMissM(DTLBMissM & ~TrapM), + .PTE, .PageType, .ITLBWriteF, .DTLBWriteM, + .HPTWReadPTE(ReadDataM), + .DCacheStallM, .HPTWAdr, .HPTWRead, .HPTWSize); + + // arbiter between IEU and hptw + + // multiplex the outputs to LSU + mux2 #(2) rwmux(MemRWM, {HPTWRead, 1'b0}, SelHPTW, PreLSURWM); + mux2 #(3) sizemux(Funct3M, HPTWSize, SelHPTW, LSUFunct3M); + mux2 #(7) funct7mux(Funct7M, 7'b0, SelHPTW, LSUFunct7M); + mux2 #(2) atomicmux(AtomicM, 2'b00, SelHPTW, LSUAtomicM); + mux2 #(12) adremux(IEUAdrE[11:0], HPTWAdr[11:0], SelHPTW, PreLSUAdrE); + mux2 #(12) replaymux(PreLSUAdrE, IEUAdrM[11:0], SelReplayCPURequest, LSUAdrE); // replay cpu request after hptw. + mux2 #(`PA_BITS) lsupadrmux(IEUAdrExtM[`PA_BITS-1:0], HPTWAdr, SelHPTW, PreLSUPAdrM); + + // always block interrupts when using the hardware page table walker. + assign CPUBusy = StallW & ~SelHPTW; + +endmodule; // lsuvirtmem