From 31d5eabd77138c4888943958704db0eec67c29f9 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 9 Nov 2022 17:52:50 -0600 Subject: [PATCH] Renamed Word to Beat for ahbcacheinterface. --- pipelined/src/cache/cache.sv | 6 +-- pipelined/src/ebu/ahbcacheinterface.sv | 26 +++++----- pipelined/src/ebu/buscachefsm.sv | 68 +++++++++++++------------- pipelined/src/ifu/ifu.sv | 5 +- pipelined/src/lsu/lsu.sv | 18 +++---- 5 files changed, 62 insertions(+), 61 deletions(-) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index dfd64684..0761728b 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -54,8 +54,8 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE // Bus fsm interface output logic [1:0] CacheBusRW, input logic CacheBusAck, - input logic SelBusWord, - input logic [LOGBWPL-1:0] WordCount, + input logic SelBusBeat, + input logic [LOGBWPL-1:0] BeatCount, input logic [LINELEN-1:0] FetchBuffer, output logic [`PA_BITS-1:0] CacheBusAdr, output logic [WORDLEN-1:0] ReadDataWord); @@ -143,7 +143,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE // like to fix this. if(DCACHE) mux2 #(LOGBWPL) WordAdrrMux(.d0(PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)]), - .d1(WordCount), .s(SelBusWord), + .d1(BeatCount), .s(SelBusBeat), .y(WordOffsetAddr)); else assign WordOffsetAddr = PAdr[$clog2(LINELEN/8) - 1 : $clog2(MUXINTERVAL/8)]; diff --git a/pipelined/src/ebu/ahbcacheinterface.sv b/pipelined/src/ebu/ahbcacheinterface.sv index 4600edcd..9b7b8f4b 100644 --- a/pipelined/src/ebu/ahbcacheinterface.sv +++ b/pipelined/src/ebu/ahbcacheinterface.sv @@ -34,7 +34,7 @@ `include "wally-config.vh" -module ahbcacheinterface #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) +module ahbcacheinterface #(parameter BEATSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) ( input logic HCLK, HRESETn, @@ -46,7 +46,7 @@ module ahbcacheinterface #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLE output logic [1:0] HTRANS, output logic HWRITE, output logic [`PA_BITS-1:0] HADDR, - output logic [LOGWPL-1:0] WordCount, + output logic [LOGWPL-1:0] BeatCount, // cache interface input logic [`PA_BITS-1:0] CacheBusAdr, @@ -61,30 +61,30 @@ module ahbcacheinterface #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLE input logic [1:0] BusRW, input logic CPUBusy, input logic [2:0] Funct3, - output logic SelBusWord, + output logic SelBusBeat, output logic BusStall, output logic BusCommitted); - localparam integer WordCountThreshold = CACHE_ENABLED ? WORDSPERLINE - 1 : 0; + localparam integer BeatCountThreshold = CACHE_ENABLED ? BEATSPERLINE - 1 : 0; logic [`PA_BITS-1:0] LocalHADDR; - logic [LOGWPL-1:0] WordCountDelayed; + logic [LOGWPL-1:0] BeatCountDelayed; logic CaptureEn; genvar index; - for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer - logic [WORDSPERLINE-1:0] CaptureWord; - assign CaptureWord[index] = CaptureEn & (index == WordCountDelayed); - flopen #(`XLEN) fb(.clk(HCLK), .en(CaptureWord[index]), .d(HRDATA), + for (index = 0; index < BEATSPERLINE; index++) begin:fetchbuffer + logic [BEATSPERLINE-1:0] CaptureBeat; + assign CaptureBeat[index] = CaptureEn & (index == BeatCountDelayed); + flopen #(`XLEN) fb(.clk(HCLK), .en(CaptureBeat[index]), .d(HRDATA), .q(FetchBuffer[(index+1)*`XLEN-1:index*`XLEN])); end mux2 #(`PA_BITS) localadrmux(PAdr, CacheBusAdr, Cacheable, LocalHADDR); - assign HADDR = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalHADDR; + assign HADDR = ({{`PA_BITS-LOGWPL{1'b0}}, BeatCount} << $clog2(`XLEN/8)) + LocalHADDR; mux2 #(3) sizemux(.d0(Funct3), .d1(`XLEN == 32 ? 3'b010 : 3'b011), .s(Cacheable), .y(HSIZE)); - buscachefsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) AHBBuscachefsm( - .HCLK, .HRESETn, .Flush, .BusRW, .CPUBusy, .BusCommitted, .BusStall, .CaptureEn, .SelBusWord, - .CacheBusRW, .CacheBusAck, .WordCount, .WordCountDelayed, + buscachefsm #(BeatCountThreshold, LOGWPL, CACHE_ENABLED) AHBBuscachefsm( + .HCLK, .HRESETn, .Flush, .BusRW, .CPUBusy, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat, + .CacheBusRW, .CacheBusAck, .BeatCount, .BeatCountDelayed, .HREADY, .HTRANS, .HWRITE, .HBURST); endmodule diff --git a/pipelined/src/ebu/buscachefsm.sv b/pipelined/src/ebu/buscachefsm.sv index 52bd4535..cddd7487 100644 --- a/pipelined/src/ebu/buscachefsm.sv +++ b/pipelined/src/ebu/buscachefsm.sv @@ -32,7 +32,7 @@ `define BURST_EN 1 // HCLK and clk must be the same clock! -module buscachefsm #(parameter integer WordCountThreshold, +module buscachefsm #(parameter integer BeatCountThreshold, parameter integer LOGWPL, parameter logic CACHE_ENABLED ) (input logic HCLK, input logic HRESETn, @@ -50,8 +50,8 @@ module buscachefsm #(parameter integer WordCountThreshold, output logic CacheBusAck, // lsu interface - output logic [LOGWPL-1:0] WordCount, WordCountDelayed, - output logic SelBusWord, + output logic [LOGWPL-1:0] BeatCount, BeatCountDelayed, + output logic SelBusBeat, // BUS interface input logic HREADY, @@ -70,11 +70,11 @@ module buscachefsm #(parameter integer WordCountThreshold, (* mark_debug = "true" *) busstatetype CurrState, NextState; - logic [LOGWPL-1:0] NextWordCount; - logic FinalWordCount; + logic [LOGWPL-1:0] NextBeatCount; + logic FinalBeatCount; logic [2:0] LocalBurstType; - logic WordCntEn; - logic WordCntReset; + logic BeatCntEn; + logic BeatCntReset; logic CacheAccess; always_ff @(posedge HCLK) @@ -91,13 +91,13 @@ module buscachefsm #(parameter integer WordCountThreshold, else NextState = DATA_PHASE; MEM3: if(CPUBusy) NextState = MEM3; else NextState = ADR_PHASE; - CACHE_FETCH: if(HREADY & FinalWordCount & CacheBusRW[0]) NextState = CACHE_WRITEBACK; - else if(HREADY & FinalWordCount & CacheBusRW[1]) NextState = CACHE_FETCH; - else if(HREADY & FinalWordCount & ~|CacheBusRW) NextState = ADR_PHASE; + CACHE_FETCH: if(HREADY & FinalBeatCount & CacheBusRW[0]) NextState = CACHE_WRITEBACK; + else if(HREADY & FinalBeatCount & CacheBusRW[1]) NextState = CACHE_FETCH; + else if(HREADY & FinalBeatCount & ~|CacheBusRW) NextState = ADR_PHASE; else NextState = CACHE_FETCH; - CACHE_WRITEBACK: if(HREADY & FinalWordCount & CacheBusRW[0]) NextState = CACHE_WRITEBACK; - else if(HREADY & FinalWordCount & CacheBusRW[1]) NextState = CACHE_FETCH; - else if(HREADY & FinalWordCount & ~|CacheBusRW) NextState = ADR_PHASE; + CACHE_WRITEBACK: if(HREADY & FinalBeatCount & CacheBusRW[0]) NextState = CACHE_WRITEBACK; + else if(HREADY & FinalBeatCount & CacheBusRW[1]) NextState = CACHE_FETCH; + else if(HREADY & FinalBeatCount & ~|CacheBusRW) NextState = ADR_PHASE; else NextState = CACHE_WRITEBACK; default: NextState = ADR_PHASE; endcase @@ -105,25 +105,25 @@ module buscachefsm #(parameter integer WordCountThreshold, // IEU, LSU, and IFU controls flopenr #(LOGWPL) - WordCountReg(.clk(HCLK), - .reset(~HRESETn | WordCntReset), - .en(WordCntEn), - .d(NextWordCount), - .q(WordCount)); + BeatCountReg(.clk(HCLK), + .reset(~HRESETn | BeatCntReset), + .en(BeatCntEn), + .d(NextBeatCount), + .q(BeatCount)); // Used to store data from data phase of AHB. flopenr #(LOGWPL) - WordCountDelayedReg(.clk(HCLK), - .reset(~HRESETn | WordCntReset), - .en(WordCntEn), - .d(WordCount), - .q(WordCountDelayed)); - assign NextWordCount = WordCount + 1'b1; + BeatCountDelayedReg(.clk(HCLK), + .reset(~HRESETn | BeatCntReset), + .en(BeatCntEn), + .d(BeatCount), + .q(BeatCountDelayed)); + assign NextBeatCount = BeatCount + 1'b1; - assign FinalWordCount = WordCountDelayed == WordCountThreshold[LOGWPL-1:0]; - assign WordCntEn = ((NextState == CACHE_WRITEBACK | NextState == CACHE_FETCH) & HREADY & ~Flush) | + assign FinalBeatCount = BeatCountDelayed == BeatCountThreshold[LOGWPL-1:0]; + assign BeatCntEn = ((NextState == CACHE_WRITEBACK | NextState == CACHE_FETCH) & HREADY & ~Flush) | (NextState == ADR_PHASE & |CacheBusRW & HREADY); - assign WordCntReset = NextState == ADR_PHASE; + assign BeatCntReset = NextState == ADR_PHASE; assign CaptureEn = (CurrState == DATA_PHASE & BusRW[1]) | (CurrState == CACHE_FETCH & HREADY); assign CacheAccess = CurrState == CACHE_FETCH | CurrState == CACHE_WRITEBACK; @@ -137,14 +137,14 @@ module buscachefsm #(parameter integer WordCountThreshold, // AHB bus interface assign HTRANS = (CurrState == ADR_PHASE & HREADY & (|BusRW | |CacheBusRW) & ~Flush) | - (CacheAccess & FinalWordCount & |CacheBusRW & HREADY) ? AHB_NONSEQ : // if we have a pipelined request - (CacheAccess & |WordCount) ? (`BURST_EN ? AHB_SEQ : AHB_NONSEQ) : AHB_IDLE; + (CacheAccess & FinalBeatCount & |CacheBusRW & HREADY) ? AHB_NONSEQ : // if we have a pipelined request + (CacheAccess & |BeatCount) ? (`BURST_EN ? AHB_SEQ : AHB_NONSEQ) : AHB_IDLE; - assign HWRITE = BusRW[0] | CacheBusRW[0] | (CurrState == CACHE_WRITEBACK & |WordCount); - assign HBURST = `BURST_EN & (|CacheBusRW | (CacheAccess & |WordCount)) ? LocalBurstType : 3'b0; + assign HWRITE = BusRW[0] | CacheBusRW[0] | (CurrState == CACHE_WRITEBACK & |BeatCount); + assign HBURST = `BURST_EN & (|CacheBusRW | (CacheAccess & |BeatCount)) ? LocalBurstType : 3'b0; always_comb begin - case(WordCountThreshold) + case(BeatCountThreshold) 0: LocalBurstType = 3'b000; 3: LocalBurstType = 3'b011; // INCR4 7: LocalBurstType = 3'b101; // INCR8 @@ -154,8 +154,8 @@ module buscachefsm #(parameter integer WordCountThreshold, end // communication to cache - assign CacheBusAck = (CacheAccess & HREADY & FinalWordCount); - assign SelBusWord = (CurrState == ADR_PHASE & (BusRW[0] | CacheBusRW[0])) | + assign CacheBusAck = (CacheAccess & HREADY & FinalBeatCount); + assign SelBusBeat = (CurrState == ADR_PHASE & (BusRW[0] | CacheBusRW[0])) | (CurrState == DATA_PHASE & BusRW[0]) | (CurrState == CACHE_WRITEBACK) | (CurrState == CACHE_FETCH); diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 93804877..41578437 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -205,6 +205,7 @@ module ifu ( assign IFURWF = 2'b10; end if (`BUS) begin : bus + // **** must fix words per line vs beats per line as in lsu. localparam integer WORDSPERLINE = `ICACHE ? `ICACHE_LINELENINBITS/`XLEN : 1; localparam integer LOGBWPL = `ICACHE ? $clog2(WORDSPERLINE) : 1; if(`ICACHE) begin : icache @@ -227,7 +228,7 @@ module ifu ( .ReadDataWord(ICacheInstrF), .SelHPTW('0), .CacheMiss(ICacheMiss), .CacheAccess(ICacheAccess), - .ByteMask('0), .WordCount('0), .SelBusWord('0), + .ByteMask('0), .BeatCount('0), .SelBusBeat('0), .FinalWriteData('0), .CacheRW(CacheRWF), .CacheAtomic('0), .FlushCache('0), @@ -239,7 +240,7 @@ module ifu ( .HRDATA, .Flush(FlushW), .CacheBusRW, .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .Funct3(3'b010), .HADDR(IFUHADDR), .HREADY(IFUHREADY), .HWRITE(IFUHWRITE), .CacheBusAdr(ICacheBusAdr), - .WordCount(), .Cacheable(CacheableF), .SelBusWord(), + .BeatCount(), .Cacheable(CacheableF), .SelBusBeat(), .CacheBusAck(ICacheBusAck), .FetchBuffer, .PAdr(PCPF), .BusRW, .CPUBusy, diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 5be7c931..b7eb3cd0 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -222,17 +222,17 @@ module lsu ( if (`BUS) begin : bus localparam integer LLENWORDSPERLINE = `DCACHE ? `DCACHE_LINELENINBITS/`LLEN : 1; localparam integer LLENLOGBWPL = `DCACHE ? $clog2(LLENWORDSPERLINE) : 1; - localparam integer AHBWWORDSPERLINE = `DCACHE ? `DCACHE_LINELENINBITS/`AHBW : 1; - localparam integer AHBWLOGBWPL = `DCACHE ? $clog2(AHBWWORDSPERLINE) : 1; + localparam integer BEATSPERLINE = `DCACHE ? `DCACHE_LINELENINBITS/`AHBW : 1; + localparam integer AHBWLOGBWPL = `DCACHE ? $clog2(BEATSPERLINE) : 1; if(`DCACHE) begin : dcache localparam integer LINELEN = `DCACHE ? `DCACHE_LINELENINBITS : `XLEN; logic [LINELEN-1:0] FetchBuffer; logic [`PA_BITS-1:0] DCacheBusAdr; logic DCacheWriteLine; logic DCacheFetchLine; - logic [AHBWLOGBWPL-1:0] WordCount; + logic [AHBWLOGBWPL-1:0] BeatCount; logic DCacheBusAck; - logic SelBusWord; + logic SelBusBeat; logic [`XLEN-1:0] PreHWDATA; //*** change name logic [`XLEN/8-1:0] ByteMaskMDelay; logic [1:0] CacheBusRW, BusRW; @@ -249,20 +249,20 @@ module lsu ( cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN), .NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`LLEN), .DCACHE(1)) dcache( - .clk, .reset, .CPUBusy, .SelBusWord, .Flush(FlushW), .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM), + .clk, .reset, .CPUBusy, .SelBusBeat, .Flush(FlushW), .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM), .FlushCache(CacheFlushM), .NextAdr(IEUAdrE[11:0]), .PAdr(PAdrM), - .ByteMask(ByteMaskM), .WordCount(WordCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]), + .ByteMask(ByteMaskM), .BeatCount(BeatCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]), .FinalWriteData(LSUWriteDataM), .SelHPTW, .CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess), .CacheCommitted(DCacheCommittedM), .CacheBusAdr(DCacheBusAdr), .ReadDataWord(DCacheReadDataWordM), .FetchBuffer, .CacheBusRW, .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0)); - ahbcacheinterface #(.WORDSPERLINE(AHBWWORDSPERLINE), .LINELEN(LINELEN), .LOGWPL(AHBWLOGBWPL), .CACHE_ENABLED(`DCACHE)) ahbcacheinterface( + ahbcacheinterface #(.BEATSPERLINE(BEATSPERLINE), .LINELEN(LINELEN), .LOGWPL(AHBWLOGBWPL), .CACHE_ENABLED(`DCACHE)) ahbcacheinterface( .HCLK(clk), .HRESETn(~reset), .Flush(FlushW), .HRDATA, .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY), - .WordCount, .SelBusWord, + .BeatCount, .SelBusBeat, .Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheBusRW, .CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdr(PAdrM), .Cacheable(CacheableOrFlushCacheM), .BusRW, .CPUBusy, @@ -284,7 +284,7 @@ module lsu ( for (index = 0; index < LLENPOVERAHBW; index++) begin:readdatalinesetsmux assign AHBWordSets[index] = DCacheReadDataWordM[(index*`AHBW)+`AHBW-1: (index*`AHBW)]; end - assign DCacheReadDataWordAHB = AHBWordSets[WordCount[$clog2(LLENPOVERAHBW)-1:0]]; + assign DCacheReadDataWordAHB = AHBWordSets[BeatCount[$clog2(LLENPOVERAHBW)-1:0]]; end else assign DCacheReadDataWordAHB = DCacheReadDataWordM[`AHBW-1:0]; mux2 #(`XLEN) LSUHWDATAMux(.d0(DCacheReadDataWordAHB), .d1(LSUWriteDataM[`AHBW-1:0]), .s(~(CacheableOrFlushCacheM)), .y(PreHWDATA));