forked from Github_Repos/cvw
Oups. I forgot to update other do files with the commands to preload the branch predictor memories.
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wally-pipelined/config/coremark/BTBPredictor.txt
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wally-pipelined/config/coremark/BTBPredictor.txt
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wally-pipelined/config/rv32ic/BTBPredictor.txt
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wally-pipelined/config/rv32ic/BTBPredictor.txt
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wally-pipelined/config/rv64ic/BTBPredictor.txt
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wally-pipelined/config/rv64ic/BTBPredictor.txt
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wally-pipelined/config/rv64icfd/BTBPredictor.txt
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wally-pipelined/config/rv64icfd/BTBPredictor.txt
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@ -30,6 +30,7 @@ def test_config(config, print_res=True):
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passed = search_log_for_text("no more .* to read", logname)
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else:
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cmd = "vsim -c >" + logname +" <<!\ndo wally-pipelined-batch-parallel.do ../config/" + config + " " + config + "\n!\n"
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print(cmd)
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os.system(cmd)
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# check for success. grep returns 0 if found, 1 if not found
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passed = search_log_for_text("All tests ran without failures", logname)
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@ -32,6 +32,15 @@ vlog +incdir+../config/busybear ../testbench/*.sv ../src/*/*.sv -suppress 2583
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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vopt +acc work.testbench_busybear -o workopt
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vsim workopt
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# load the branch predictors with known data. The value of the data is not important for function, but
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# is important for perventing pessimistic x propagation.
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mem load -infile twoBitPredictor.txt -format bin testbench/dut/hart/ifu/bpred/DirPredictor/memory/memory
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switch $argc {
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0 {mem load -infile ../config/rv64ic/BTBPredictor.txt -format bin testbench/dut/hart/ifu/bpred/TargetPredictor/memory/memory}
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1 {mem load -infile ../config/$1/BTBPredictor.txt -format bin testbench/dut/hart/ifu/bpred/TargetPredictor/memory/memory}
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}
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view wave
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@ -35,6 +35,14 @@ vlog +incdir+../config/coremark ../testbench/testbench-coremark.sv ../src/*/*.sv
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vopt +acc work.testbench -o workopt
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vsim workopt
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# load the branch predictors with known data. The value of the data is not important for function, but
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# is important for perventing pessimistic x propagation.
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mem load -infile twoBitPredictor.txt -format bin testbench/dut/hart/ifu/bpred/DirPredictor/memory/memory
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switch $argc {
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0 {mem load -infile ../config/rv64ic/BTBPredictor.txt -format bin testbench/dut/hart/ifu/bpred/TargetPredictor/memory/memory}
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1 {mem load -infile ../config/$1/BTBPredictor.txt -format bin testbench/dut/hart/ifu/bpred/TargetPredictor/memory/memory}
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}
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view wave
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-- display input and output signals as hexidecimal values
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@ -38,6 +38,14 @@ switch $argc {
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vopt +acc work.testbench -o workopt
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vsim workopt
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# load the branch predictors with known data. The value of the data is not important for function, but
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# is important for perventing pessimistic x propagation.
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mem load -infile twoBitPredictor.txt -format bin testbench/dut/hart/ifu/bpred/DirPredictor/memory/memory
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switch $argc {
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0 {mem load -infile ../config/rv64ic/BTBPredictor.txt -format bin testbench/dut/hart/ifu/bpred/TargetPredictor/memory/memory}
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1 {mem load -infile ../config/$1/BTBPredictor.txt -format bin testbench/dut/hart/ifu/bpred/TargetPredictor/memory/memory}
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}
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view wave
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-- display input and output signals as hexidecimal values
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@ -34,5 +34,10 @@ vlog +incdir+$1 ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583
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vopt work.testbench -o workopt
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vsim workopt
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# load the branch predictors with known data. The value of the data is not important for function, but
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# is important for perventing pessimistic x propagation.
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mem load -infile twoBitPredictor.txt -format bin testbench/dut/hart/ifu/bpred/DirPredictor/memory/memory
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mem load -infile BTBPredictor.txt -format bin testbench/dut/hart/ifu/bpred/TargetPredictor/memory/memory
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run -all
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quit
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@ -31,8 +31,17 @@ vlog +incdir+$1 ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583
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# start and run simulation
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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vopt work.testbench -o workopt
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vopt +acc=+/testbench/dut/hart/ifu/bpred/DirPredictor/memory/memory +acc=+/testbench/dut/hart/ifu/bpred/TargetPredictor/memory/memory work.testbench -o workopt
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vsim workopt
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# load the branch predictors with known data. The value of the data is not important for function, but
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# is important for perventing pessimistic x propagation.
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mem load -infile twoBitPredictor.txt -format bin testbench/dut/hart/ifu/bpred/DirPredictor/memory/memory
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switch $argc {
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0 {mem load -infile ../config/rv64ic/BTBPredictor.txt -format bin testbench/dut/hart/ifu/bpred/TargetPredictor/memory/memory}
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1 {mem load -infile ../config/$1/BTBPredictor.txt -format bin testbench/dut/hart/ifu/bpred/TargetPredictor/memory/memory}
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}
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run -all
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quit
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@ -41,7 +41,10 @@ vsim workopt
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# load the branch predictors with known data. The value of the data is not important for function, but
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# is important for perventing pessimistic x propagation.
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mem load -infile twoBitPredictor.txt -format bin testbench/dut/hart/ifu/bpred/DirPredictor/memory/memory
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mem load -infile BTBPredictor.txt -format bin testbench/dut/hart/ifu/bpred/TargetPredictor/memory/memory
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switch $argc {
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0 {mem load -infile ../config/rv64ic/BTBPredictor.txt -format bin testbench/dut/hart/ifu/bpred/TargetPredictor/memory/memory}
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1 {mem load -infile ../config/$1/BTBPredictor.txt -format bin testbench/dut/hart/ifu/bpred/TargetPredictor/memory/memory}
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}
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do wave.do
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add log -r /*
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@ -41,7 +41,10 @@ vsim workopt
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# load the branch predictors with known data. The value of the data is not important for function, but
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# is important for perventing pessimistic x propagation.
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mem load -infile twoBitPredictor.txt -format bin testbench/dut/hart/ifu/bpred/DirPredictor/memory/memory
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mem load -infile BTBPredictor.txt -format bin testbench/dut/hart/ifu/bpred/TargetPredictor/memory/memory
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switch $argc {
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0 {mem load -infile ../config/rv64ic/BTBPredictor.txt -format bin testbench/dut/hart/ifu/bpred/TargetPredictor/memory/memory}
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1 {mem load -infile ../config/$1/BTBPredictor.txt -format bin testbench/dut/hart/ifu/bpred/TargetPredictor/memory/memory}
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}
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view wave
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@ -91,7 +91,7 @@ module BTBPredictor
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.WA1(UpdatePCIndex),
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.WD1({UpdateInstrClass, UpdateTarget}),
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.WEN1(UpdateEN),
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.BitWEN1({`XLEN{1'b1}}));
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.BitWEN1({4'b0000, {`XLEN{1'b1}}})); // *** definitely not right.
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endmodule
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