forked from Github_Repos/cvw
		
	hptw: Removed NonBusTrapM from LSU
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				@ -56,7 +56,6 @@ module lsu
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   input logic [1:0] 	       PrivilegeModeW,
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					   input logic [1:0] 	       PrivilegeModeW,
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   input logic 		       DTLBFlushM,
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					   input logic 		       DTLBFlushM,
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   // faults
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					   // faults
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   input logic 		       NonBusTrapM, 
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   output logic 	       DTLBLoadPageFaultM, DTLBStorePageFaultM,
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					   output logic 	       DTLBLoadPageFaultM, DTLBStorePageFaultM,
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   output logic 	       LoadMisalignedFaultM, LoadAccessFaultM,
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					   output logic 	       LoadMisalignedFaultM, LoadAccessFaultM,
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   // cpu hazard unit (trap)
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					   // cpu hazard unit (trap)
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@ -36,7 +36,7 @@ module privileged (
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  input  logic [31:0]      InstrD, InstrE, InstrM, InstrW,
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					  input  logic [31:0]      InstrD, InstrE, InstrM, InstrW,
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  output logic [`XLEN-1:0] CSRReadValW,
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					  output logic [`XLEN-1:0] CSRReadValW,
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  output logic [`XLEN-1:0] PrivilegedNextPCM,
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					  output logic [`XLEN-1:0] PrivilegedNextPCM,
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  output logic             RetM, TrapM, NonBusTrapM,
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					  output logic             RetM, TrapM, 
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  output logic             ITLBFlushF, DTLBFlushM,
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					  output logic             ITLBFlushF, DTLBFlushM,
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  input  logic             InstrValidM, CommittedM,
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					  input  logic             InstrValidM, CommittedM,
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  input  logic             FRegWriteM, LoadStallD,
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					  input  logic             FRegWriteM, LoadStallD,
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@ -42,7 +42,7 @@ module trap (
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  input logic [31:0] 	   InstrM,
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					  input logic [31:0] 	   InstrM,
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  input logic 		   StallW,
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					  input logic 		   StallW,
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  input logic 		   InstrValidM, CommittedM,
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					  input logic 		   InstrValidM, CommittedM,
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  output logic 		   NonBusTrapM, TrapM, MTrapM, STrapM, UTrapM, RetM,
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					  output logic 		   TrapM, MTrapM, STrapM, UTrapM, RetM,
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  output logic 		   InterruptM,
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					  output logic 		   InterruptM,
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  output logic 		   ExceptionM,
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					  output logic 		   ExceptionM,
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  output logic 		   PendingInterruptM,
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					  output logic 		   PendingInterruptM,
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@ -56,7 +56,7 @@ module trap (
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  logic [11:0] PendingIntsM; 
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					  logic [11:0] PendingIntsM; 
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  //logic InterruptM;
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					  //logic InterruptM;
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  logic [`XLEN-1:0] PrivilegedTrapVector, PrivilegedVectoredTrapVector;
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					  logic [`XLEN-1:0] PrivilegedTrapVector, PrivilegedVectoredTrapVector;
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  logic BusTrapM;
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					  logic NonBusTrapM, BusTrapM;
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  // Determine pending enabled interrupts
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					  // Determine pending enabled interrupts
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  assign MIntGlobalEnM = (PrivilegeModeW != `M_MODE) || STATUS_MIE; // if M ints enabled or lower priv 3.1.9
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					  assign MIntGlobalEnM = (PrivilegeModeW != `M_MODE) || STATUS_MIE; // if M ints enabled or lower priv 3.1.9
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@ -58,7 +58,7 @@ module wallypipelinedhart
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  //  logic [1:0]  ForwardAE, ForwardBE;
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					  //  logic [1:0]  ForwardAE, ForwardBE;
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  logic 		    StallF, StallD, StallE, StallM, StallW;
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					  logic 		    StallF, StallD, StallE, StallM, StallW;
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  logic 		    FlushF, FlushD, FlushE, FlushM, FlushW;
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					  logic 		    FlushF, FlushD, FlushE, FlushM, FlushW;
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  logic 		    RetM, TrapM, NonBusTrapM;
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					  logic 		    RetM, TrapM;
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  // new signals that must connect through DP
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					  // new signals that must connect through DP
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  logic 		    MulDivE, W64E;
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					  logic 		    MulDivE, W64E;
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@ -215,7 +215,6 @@ module wallypipelinedhart
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	  .STATUS_MPP(STATUS_MPP),  // from csr	  
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						  .STATUS_MPP(STATUS_MPP),  // from csr	  
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	  .DTLBFlushM(DTLBFlushM),                   // connects to privilege
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						  .DTLBFlushM(DTLBFlushM),                   // connects to privilege
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	  .NonBusTrapM(NonBusTrapM),                 // connects to privilege
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	  .DTLBLoadPageFaultM(DTLBLoadPageFaultM),   // connects to privilege
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						  .DTLBLoadPageFaultM(DTLBLoadPageFaultM),   // connects to privilege
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	  .DTLBStorePageFaultM(DTLBStorePageFaultM), // connects to privilege
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						  .DTLBStorePageFaultM(DTLBStorePageFaultM), // connects to privilege
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	  .LoadMisalignedFaultM(LoadMisalignedFaultM), // connects to privilege
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						  .LoadMisalignedFaultM(LoadMisalignedFaultM), // connects to privilege
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