From 2f81e4c70d4000ea477fb5146cd0f3ea5dbb5812 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 17 Jul 2021 15:22:24 -0400
Subject: [PATCH] hptw: Removed NonBusTrapM from LSU

---
 wally-pipelined/src/lsu/lsu.sv                  | 1 -
 wally-pipelined/src/privileged/privileged.sv    | 2 +-
 wally-pipelined/src/privileged/trap.sv          | 4 ++--
 wally-pipelined/src/wally/wallypipelinedhart.sv | 3 +--
 4 files changed, 4 insertions(+), 6 deletions(-)

diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv
index fd65dcb2..d138a933 100644
--- a/wally-pipelined/src/lsu/lsu.sv
+++ b/wally-pipelined/src/lsu/lsu.sv
@@ -56,7 +56,6 @@ module lsu
    input logic [1:0] 	       PrivilegeModeW,
    input logic 		       DTLBFlushM,
    // faults
-   input logic 		       NonBusTrapM, 
    output logic 	       DTLBLoadPageFaultM, DTLBStorePageFaultM,
    output logic 	       LoadMisalignedFaultM, LoadAccessFaultM,
    // cpu hazard unit (trap)
diff --git a/wally-pipelined/src/privileged/privileged.sv b/wally-pipelined/src/privileged/privileged.sv
index d982b904..70d5ad0d 100644
--- a/wally-pipelined/src/privileged/privileged.sv
+++ b/wally-pipelined/src/privileged/privileged.sv
@@ -36,7 +36,7 @@ module privileged (
   input  logic [31:0]      InstrD, InstrE, InstrM, InstrW,
   output logic [`XLEN-1:0] CSRReadValW,
   output logic [`XLEN-1:0] PrivilegedNextPCM,
-  output logic             RetM, TrapM, NonBusTrapM,
+  output logic             RetM, TrapM, 
   output logic             ITLBFlushF, DTLBFlushM,
   input  logic             InstrValidM, CommittedM,
   input  logic             FRegWriteM, LoadStallD,
diff --git a/wally-pipelined/src/privileged/trap.sv b/wally-pipelined/src/privileged/trap.sv
index 7462353d..ea50fddc 100644
--- a/wally-pipelined/src/privileged/trap.sv
+++ b/wally-pipelined/src/privileged/trap.sv
@@ -42,7 +42,7 @@ module trap (
   input logic [31:0] 	   InstrM,
   input logic 		   StallW,
   input logic 		   InstrValidM, CommittedM,
-  output logic 		   NonBusTrapM, TrapM, MTrapM, STrapM, UTrapM, RetM,
+  output logic 		   TrapM, MTrapM, STrapM, UTrapM, RetM,
   output logic 		   InterruptM,
   output logic 		   ExceptionM,
   output logic 		   PendingInterruptM,
@@ -56,7 +56,7 @@ module trap (
   logic [11:0] PendingIntsM; 
   //logic InterruptM;
   logic [`XLEN-1:0] PrivilegedTrapVector, PrivilegedVectoredTrapVector;
-  logic BusTrapM;
+  logic NonBusTrapM, BusTrapM;
 
   // Determine pending enabled interrupts
   assign MIntGlobalEnM = (PrivilegeModeW != `M_MODE) || STATUS_MIE; // if M ints enabled or lower priv 3.1.9
diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv
index 77800bc8..0736295e 100644
--- a/wally-pipelined/src/wally/wallypipelinedhart.sv
+++ b/wally-pipelined/src/wally/wallypipelinedhart.sv
@@ -58,7 +58,7 @@ module wallypipelinedhart
   //  logic [1:0]  ForwardAE, ForwardBE;
   logic 		    StallF, StallD, StallE, StallM, StallW;
   logic 		    FlushF, FlushD, FlushE, FlushM, FlushW;
-  logic 		    RetM, TrapM, NonBusTrapM;
+  logic 		    RetM, TrapM;
 
   // new signals that must connect through DP
   logic 		    MulDivE, W64E;
@@ -215,7 +215,6 @@ module wallypipelinedhart
 	  .STATUS_MPP(STATUS_MPP),  // from csr	  
 
 	  .DTLBFlushM(DTLBFlushM),                   // connects to privilege
-	  .NonBusTrapM(NonBusTrapM),                 // connects to privilege
 	  .DTLBLoadPageFaultM(DTLBLoadPageFaultM),   // connects to privilege
 	  .DTLBStorePageFaultM(DTLBStorePageFaultM), // connects to privilege
 	  .LoadMisalignedFaultM(LoadMisalignedFaultM), // connects to privilege