forked from Github_Repos/cvw
Updates to muldiv.sv for 32-bit div/rem
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@ -31,7 +31,7 @@
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`define XLEN 64
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`define XLEN 64
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// MISA RISC-V configuration per specification
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// MISA RISC-V configuration per specification
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`define MISA (32'h00000104 | 0 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
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`define MISA (32'h00000104 | 0 << 5 | 0 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
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`define A_SUPPORTED ((`MISA >> 0) % 2 == 1)
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`define A_SUPPORTED ((`MISA >> 0) % 2 == 1)
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`define C_SUPPORTED ((`MISA >> 2) % 2 == 1)
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`define C_SUPPORTED ((`MISA >> 2) % 2 == 1)
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`define D_SUPPORTED ((`MISA >> 3) % 2 == 1)
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`define D_SUPPORTED ((`MISA >> 3) % 2 == 1)
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@ -76,7 +76,7 @@ module muldiv (
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assign Den0 = W64E ? {{32{SrcBE[31]&signedDivide}}, SrcBE[31:0]} : SrcBE;
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assign Den0 = W64E ? {{32{SrcBE[31]&signedDivide}}, SrcBE[31:0]} : SrcBE;
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end else begin // RV32 has no W-type instructions
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end else begin // RV32 has no W-type instructions
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assign Num0 = SrcAE;
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assign Num0 = SrcAE;
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assign Den0 = SrcAE;
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assign Den0 = SrcBE;
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end
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end
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// capture the Numerator/Denominator
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// capture the Numerator/Denominator
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@ -320,11 +320,11 @@ string tests32f[] = '{
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"rv32m/I-MUL-01", "2000",
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"rv32m/I-MUL-01", "2000",
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"rv32m/I-MULH-01", "2000",
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"rv32m/I-MULH-01", "2000",
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"rv32m/I-MULHSU-01", "2000",
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"rv32m/I-MULHSU-01", "2000",
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"rv32m/I-MULHU-01", "2000"
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"rv32m/I-MULHU-01", "2000",
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//"rv32m/I-DIV-01", "2000",
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"rv32m/I-DIV-01", "2000",
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//"rv32m/I-DIVU-01", "2000",
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"rv32m/I-DIVU-01", "2000",
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//"rv32m/I-REM-01", "2000",
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"rv32m/I-REM-01", "2000",
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//"rv32m/I-REMU-01", "2000"
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"rv32m/I-REMU-01", "2000"
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};
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};
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string tests32ic[] = '{
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string tests32ic[] = '{
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