From 2eeb12c6741659ece6bc5e17d13ccbd04dbfc6c5 Mon Sep 17 00:00:00 2001
From: "James E. Stine" <james.stine@okstate.edu>
Date: Tue, 1 Jun 2021 15:31:07 -0400
Subject: [PATCH] Updates to muldiv.sv for 32-bit div/rem

---
 wally-pipelined/config/rv64ic/wally-config.vh  |  2 +-
 wally-pipelined/src/muldiv/muldiv.sv           |  2 +-
 wally-pipelined/testbench/testbench-imperas.sv | 10 +++++-----
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/wally-pipelined/config/rv64ic/wally-config.vh b/wally-pipelined/config/rv64ic/wally-config.vh
index 259e41ae..12d254ba 100644
--- a/wally-pipelined/config/rv64ic/wally-config.vh
+++ b/wally-pipelined/config/rv64ic/wally-config.vh
@@ -31,7 +31,7 @@
 `define XLEN 64
 
 // MISA RISC-V configuration per specification
-`define MISA (32'h00000104 | 0 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
+`define MISA (32'h00000104 | 0 << 5 | 0 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
 `define A_SUPPORTED ((`MISA >> 0) % 2 == 1)
 `define C_SUPPORTED ((`MISA >> 2) % 2 == 1)
 `define D_SUPPORTED ((`MISA >> 3) % 2 == 1)
diff --git a/wally-pipelined/src/muldiv/muldiv.sv b/wally-pipelined/src/muldiv/muldiv.sv
index 0c26a5df..e10b0c55 100644
--- a/wally-pipelined/src/muldiv/muldiv.sv
+++ b/wally-pipelined/src/muldiv/muldiv.sv
@@ -76,7 +76,7 @@ module muldiv (
             assign Den0 = W64E ? {{32{SrcBE[31]&signedDivide}}, SrcBE[31:0]} : SrcBE;
 	 end else begin // RV32 has no W-type instructions
             assign Num0 = SrcAE;
-            assign Den0 = SrcAE;	    
+            assign Den0 = SrcBE;	    
 	 end	    
 
 	 // capture the Numerator/Denominator	 
diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv
index c60aa40d..dabc6d12 100644
--- a/wally-pipelined/testbench/testbench-imperas.sv
+++ b/wally-pipelined/testbench/testbench-imperas.sv
@@ -320,11 +320,11 @@ string tests32f[] = '{
     "rv32m/I-MUL-01", "2000",
     "rv32m/I-MULH-01", "2000",
     "rv32m/I-MULHSU-01", "2000",
-    "rv32m/I-MULHU-01", "2000"
-    //"rv32m/I-DIV-01", "2000",
-    //"rv32m/I-DIVU-01", "2000",
-    //"rv32m/I-REM-01", "2000",
-    //"rv32m/I-REMU-01", "2000"
+    "rv32m/I-MULHU-01", "2000",
+    "rv32m/I-DIV-01", "2000",
+    "rv32m/I-DIVU-01", "2000",
+    "rv32m/I-REM-01", "2000",
+    "rv32m/I-REMU-01", "2000"
   };
 
   string tests32ic[] = '{