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Removed unused signals

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David Harris 2022-09-12 11:35:35 -07:00
parent f45bb25618
commit 2babf1fd7a
1 changed files with 0 additions and 2 deletions
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pipelined/src/fpu/fdivsqrt.sv
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@ -55,13 +55,11 @@ module fdivsqrt(
logic [`DIVb+3:0] NextWSN, NextWCN;
logic [`DIVb+3:0] WS, WC;
logic [`DIVb+3:0] StickyWSA;
logic [`DIVb:0] X;
logic [`DIVN-2:0] D; // U0.N-1
logic [`DIVN-2:0] Dpreproc;
logic [`DIVb:0] FirstS, FirstSM, FirstQ, FirstQM;
logic [`DIVb-1:0] FirstC;
logic NegSticky;
logic Firstqn;
logic WZero;