diff --git a/pipelined/src/fpu/fdivsqrt.sv b/pipelined/src/fpu/fdivsqrt.sv
index abf20bef..3fcc8122 100644
--- a/pipelined/src/fpu/fdivsqrt.sv
+++ b/pipelined/src/fpu/fdivsqrt.sv
@@ -55,13 +55,11 @@ module fdivsqrt(
 
   logic [`DIVb+3:0]  NextWSN, NextWCN;
   logic [`DIVb+3:0]  WS, WC;
-  logic [`DIVb+3:0] StickyWSA;
   logic [`DIVb:0] X;
   logic [`DIVN-2:0]  D; // U0.N-1
   logic [`DIVN-2:0] Dpreproc;
   logic [`DIVb:0] FirstS, FirstSM, FirstQ, FirstQM;
   logic [`DIVb-1:0] FirstC;
-  logic NegSticky;
   logic Firstqn;
   logic WZero;