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Added buffered signals for int/fp

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cturek 2022-10-28 21:47:24 +00:00
parent f81d1e15b6
commit 2a45787b37
1 changed files with 3 additions and 3 deletions
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pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
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@ -53,15 +53,15 @@ module fdivsqrtpreproc (
logic [$clog2(`NF+2)-1:0] XZeroCnt, YZeroCnt; logic [$clog2(`NF+2)-1:0] XZeroCnt, YZeroCnt;
logic [`NE+1:0] Qe; logic [`NE+1:0] Qe;
// Intdiv signals // Intdiv signals
// logic [`DIVN-1:0] ZeroBufX, ZeroBufY; add after Cedar Commit logic [`DIVN-1:0] ZeroBufX, ZeroBufY;
logic [`XLEN-1:0] PosA, PosB; logic [`XLEN-1:0] PosA, PosB;
logic Signed, Aneg, Bneg; logic Signed, Aneg, Bneg;
// ***can probably merge X LZC with conversion // ***can probably merge X LZC with conversion
// cout the number of leading zeros // cout the number of leading zeros
// Muxes needed for Int; add after Cedar Commit // Muxes needed for Int; add after Cedar Commit
// assign ZeroBufX = Int ? {ForwardedSrcAE, {`DIVN-`XLEN{1'b0}}} : {Xm, {`DIVN-`NF{1'b0}}}; assign ZeroBufX = MDUE ? {ForwardedSrcAE, {`DIVN-`XLEN{1'b0}}} : {Xm, {`DIVN-`NF-1{1'b0}}};
// assign ZeroBufY = Int ? {ForwardedSrcBE, {`DIVN-`XLEN{1'b0}}} : {Ym, {`DIVN-`NF{1'b0}}}; assign ZeroBufY = MDUE ? {ForwardedSrcBE, {`DIVN-`XLEN{1'b0}}} : {Ym, {`DIVN-`NF-1{1'b0}}};
lzc #(`NF+1) lzcX (Xm, XZeroCnt); lzc #(`NF+1) lzcX (Xm, XZeroCnt);
lzc #(`NF+1) lzcY (Ym, YZeroCnt); lzc #(`NF+1) lzcY (Ym, YZeroCnt);