From 2a45787b377513d89dda9db3ee6b766e40c50be8 Mon Sep 17 00:00:00 2001
From: cturek <cturek@hmc.edu>
Date: Fri, 28 Oct 2022 21:47:24 +0000
Subject: [PATCH] Added buffered signals for int/fp

---
 pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
index e6fe1a79..f1882ad6 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
@@ -53,15 +53,15 @@ module fdivsqrtpreproc (
   logic  [$clog2(`NF+2)-1:0] XZeroCnt, YZeroCnt;
   logic  [`NE+1:0] Qe;
   // Intdiv signals
-  // logic  [`DIVN-1:0] ZeroBufX, ZeroBufY; add after Cedar Commit
+  logic  [`DIVN-1:0] ZeroBufX, ZeroBufY;
   logic  [`XLEN-1:0] PosA, PosB;
   logic  Signed, Aneg, Bneg;
 
   // ***can probably merge X LZC with conversion
   // cout the number of leading zeros
   // Muxes needed for Int; add after Cedar Commit
-  // assign ZeroBufX = Int ? {ForwardedSrcAE, {`DIVN-`XLEN{1'b0}}} : {Xm, {`DIVN-`NF{1'b0}}};
-  // assign ZeroBufY = Int ? {ForwardedSrcBE, {`DIVN-`XLEN{1'b0}}} : {Ym, {`DIVN-`NF{1'b0}}};
+  assign ZeroBufX = MDUE ? {ForwardedSrcAE, {`DIVN-`XLEN{1'b0}}} : {Xm, {`DIVN-`NF-1{1'b0}}};
+  assign ZeroBufY = MDUE ? {ForwardedSrcBE, {`DIVN-`XLEN{1'b0}}} : {Ym, {`DIVN-`NF-1{1'b0}}};
   lzc #(`NF+1) lzcX (Xm, XZeroCnt);
   lzc #(`NF+1) lzcY (Ym, YZeroCnt);