diff --git a/src/fpu/fdivsqrt/fdivsqrtfgen2.sv b/src/fpu/fdivsqrt/fdivsqrtfgen2.sv
index 9c13a91d..250fb4fb 100644
--- a/src/fpu/fdivsqrt/fdivsqrtfgen2.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtfgen2.sv
@@ -29,7 +29,7 @@
 `include "wally-config.vh"
 
 module fdivsqrtfgen2 (
-  input  logic up, uz,
+  input  logic             up, uz,
   input  logic [`DIVb+3:0] C, U, UM,
   output logic [`DIVb+3:0] F
 );
diff --git a/src/fpu/fdivsqrt/fdivsqrtfgen4.sv b/src/fpu/fdivsqrt/fdivsqrtfgen4.sv
index 975d58eb..a07e504f 100644
--- a/src/fpu/fdivsqrt/fdivsqrtfgen4.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtfgen4.sv
@@ -29,7 +29,7 @@
 `include "wally-config.vh"
 
 module fdivsqrtfgen4 (
-  input  logic [3:0] udigit,
+  input  logic [3:0]       udigit,
   input  logic [`DIVb+3:0] C, U, UM,
   output logic [`DIVb+3:0] F
 );
diff --git a/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/src/fpu/fdivsqrt/fdivsqrtfsm.sv
index 4cfede60..559e4b77 100644
--- a/src/fpu/fdivsqrt/fdivsqrtfsm.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtfsm.sv
@@ -29,24 +29,24 @@
 `include "wally-config.vh"
 
 module fdivsqrtfsm(
-  input  logic clk, 
-  input  logic reset, 
+  input  logic                clk, 
+  input  logic                reset, 
   input  logic [`FMTBITS-1:0] FmtE,
-  input  logic XInfE, YInfE, 
-  input  logic XZeroE, YZeroE, 
-  input  logic XNaNE, YNaNE, 
-  input  logic FDivStartE, IDivStartE,
-  input  logic XsE,
-  input  logic SqrtE,
-  input  logic StallM,
-  input  logic FlushE,
-  input  logic WZeroE,
-  input  logic IntDivE,
-  input  logic [`DIVBLEN:0] nE,
-  input  logic ISpecialCaseE,
-  output logic IFDivStartE,
-  output logic FDivBusyE, FDivDoneE,
-  output logic SpecialCaseM
+  input  logic                XInfE, YInfE, 
+  input  logic                XZeroE, YZeroE, 
+  input  logic                XNaNE, YNaNE, 
+  input  logic                FDivStartE, IDivStartE,
+  input  logic                XsE,
+  input  logic                SqrtE,
+  input  logic                StallM,
+  input  logic                FlushE,
+  input  logic                WZeroE,
+  input  logic                IntDivE,
+  input  logic [`DIVBLEN:0]   nE,
+  input  logic                ISpecialCaseE,
+  output logic                IFDivStartE,
+  output logic                FDivBusyE, FDivDoneE,
+  output logic                SpecialCaseM
 );
   
   typedef enum logic [1:0] {IDLE, BUSY, DONE} statetype;
diff --git a/src/fpu/fdivsqrt/fdivsqrtiter.sv b/src/fpu/fdivsqrt/fdivsqrtiter.sv
index 7de120ed..ec15423e 100644
--- a/src/fpu/fdivsqrt/fdivsqrtiter.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtiter.sv
@@ -29,10 +29,10 @@
 `include "wally-config.vh"
 
 module fdivsqrtiter(
-  input  logic clk,
-  input  logic IFDivStartE, 
-  input  logic FDivBusyE, 
-  input  logic SqrtE,
+  input  logic             clk,
+  input  logic             IFDivStartE, 
+  input  logic             FDivBusyE, 
+  input  logic             SqrtE,
   input  logic [`DIVb+3:0] X,
   input  logic [`DIVb-1:0] DPreproc,
   output logic [`DIVb-1:0] D,
diff --git a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
index 7b92f8c8..b8575f7f 100644
--- a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
@@ -112,7 +112,7 @@ module fdivsqrtpostproc(
 
     // Select quotient or remainder and do normalization shift
     mux2 #(`DIVBLEN+1) normshiftmux(((`DIVBLEN+1)'(`DIVb) - (nM * (`DIVBLEN+1)'(`LOGR))), (mM + (`DIVBLEN+1)'(`DIVa)), RemOpM, NormShiftM);
-    mux2 #(`DIVb+4)   presresultmux(NormQuotM, NormRemM, RemOpM, PreResultM);
+    mux2 #(`DIVb+4)    presresultmux(NormQuotM, NormRemM, RemOpM, PreResultM);
     assign PreIntResultM = $signed(PreResultM >>> NormShiftM); 
 
     // special case logic
diff --git a/src/fpu/fdivsqrt/fdivsqrtqsel2.sv b/src/fpu/fdivsqrt/fdivsqrtqsel2.sv
index fd0a2a46..18c577b9 100644
--- a/src/fpu/fdivsqrt/fdivsqrtqsel2.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtqsel2.sv
@@ -30,7 +30,7 @@
 
 module fdivsqrtqsel2 ( 
   input  logic [3:0] ps, pc, 
-  output logic  up, uz, un
+  output logic       up, uz, un
 );
  
   logic [3:0]  p, g;
diff --git a/src/fpu/fdivsqrt/fdivsqrtstage4.sv b/src/fpu/fdivsqrt/fdivsqrtstage4.sv
index ee92d263..f2ff3734 100644
--- a/src/fpu/fdivsqrt/fdivsqrtstage4.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtstage4.sv
@@ -31,7 +31,7 @@
 module fdivsqrtstage4 (
   input  logic [`DIVb-1:0] D,
   input  logic [`DIVb+3:0] DBar, D2, DBar2,
-  input  logic [`DIVb:0] U,UM,
+  input  logic [`DIVb:0]   U,UM,
   input  logic [`DIVb+3:0] WS, WC,
   input  logic [`DIVb+1:0] C,
   input  logic             SqrtE, j1,
@@ -58,8 +58,8 @@ module fdivsqrtstage4 (
   // 0000 =  0
   // 0010 = -1
   // 0001 = -2
-  assign Smsbs = U[`DIVb:`DIVb-4];
-  assign Dmsbs = D[`DIVb-1:`DIVb-3];
+  assign Smsbs  = U[`DIVb:`DIVb-4];
+  assign Dmsbs  = D[`DIVb-1:`DIVb-3];
   assign WCmsbs = WC[`DIVb+3:`DIVb-4];
   assign WSmsbs = WS[`DIVb+3:`DIVb-4];
 
diff --git a/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv b/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv
index 65b8940a..33956a0f 100644
--- a/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv
+++ b/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv
@@ -32,10 +32,10 @@
 // Unified OTFC, Radix 2 //
 ///////////////////////////////
 module fdivsqrtuotfc2(
-  input  logic         up, un,
+  input  logic             up, un,
   input  logic [`DIVb+1:0] C,
-  input logic [`DIVb:0] U, UM,
-  output logic [`DIVb:0] UNext, UMNext
+  input  logic [`DIVb:0]   U, UM,
+  output logic [`DIVb:0]   UNext, UMNext
 );
   //  The on-the-fly converter transfers the divsqrt
   //  bits to the quotient as they come.