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Disabled AHB burst mode, which discovered a bug.

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Multimanger bug in how back to back requests were arbitrated.
This commit is contained in:
Ross Thompson 2022-09-03 22:31:41 -05:00
parent bd37a5c6dc
commit 26bfaddb25
2 changed files with 10 additions and 5 deletions
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7
pipelined/src/ebu/ahbmultimanager.sv
View File

@ -145,7 +145,7 @@ module ahbmultimanager
case (CurrState)
IDLE: if (both) NextState = ARBITRATE;
else NextState = IDLE;
ARBITRATE: if (HREADY & FinalBeat) NextState = IDLE;
ARBITRATE: if (HREADY & FinalBeat & ~(LSUReq & IFUReq)) NextState = IDLE;
else NextState = ARBITRATE;
default: NextState = IDLE;
endcase
@ -153,7 +153,7 @@ module ahbmultimanager
// Manager needs to count beats.
flopenr #(4)
BeatCountReg(.clk(HCLK),
.reset(~HRESETn | CntReset),
.reset(~HRESETn | CntReset | FinalBeat),
.en(BeatCntEn),
.d(NextBeatCount),
.q(BeatCount));
@ -189,6 +189,9 @@ module ahbmultimanager
// basic arb always selects LSU when both
// replace this block for more sophisticated arbitration.
// Manager 0 (IFU)
// this logic is all wrong.
// test by removing burst.
// 2nd want to test with slower memory.
assign save[0] = CurrState == IDLE & both;
assign restore[0] = CurrState == ARBITRATE;
assign dis[0] = CurrState == ARBITRATE;

8
pipelined/src/ebu/buscachefsm.sv
View File

@ -136,10 +136,12 @@ module buscachefsm #(parameter integer WordCountThreshold,
// AHB bus interface
assign HTRANS = (CurrState == ADR_PHASE & HREADY & (|RW | |CacheRW)) |
(CurrState == DATA_PHASE & ~HREADY) ? AHB_NONSEQ :
(CacheAccess & |WordCount) ? AHB_SEQ : AHB_IDLE;
// (CacheAccess & |WordCount) ? AHB_SEQ : AHB_IDLE;
(CacheAccess & |WordCount) ? AHB_NONSEQ : AHB_IDLE;
assign HWRITE = RW[0] | CacheRW[0];
assign HBURST = (|CacheRW) ? LocalBurstType : 3'b0;
// assign HBURST = (|CacheRW) ? LocalBurstType : 3'b0;
// try disabling burst as it is not working with the fpga.
assign HBURST = 3'b0;
always_comb begin
case(WordCountThreshold)