From 26bfaddb25991b02179ae6116d137bf76a4c623e Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 3 Sep 2022 22:31:41 -0500 Subject: [PATCH] Disabled AHB burst mode, which discovered a bug. Multimanger bug in how back to back requests were arbitrated. --- pipelined/src/ebu/ahbmultimanager.sv | 7 +++++-- pipelined/src/ebu/buscachefsm.sv | 8 +++++--- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/pipelined/src/ebu/ahbmultimanager.sv b/pipelined/src/ebu/ahbmultimanager.sv index c3085af8..80fd41c0 100644 --- a/pipelined/src/ebu/ahbmultimanager.sv +++ b/pipelined/src/ebu/ahbmultimanager.sv @@ -145,7 +145,7 @@ module ahbmultimanager case (CurrState) IDLE: if (both) NextState = ARBITRATE; else NextState = IDLE; - ARBITRATE: if (HREADY & FinalBeat) NextState = IDLE; + ARBITRATE: if (HREADY & FinalBeat & ~(LSUReq & IFUReq)) NextState = IDLE; else NextState = ARBITRATE; default: NextState = IDLE; endcase @@ -153,7 +153,7 @@ module ahbmultimanager // Manager needs to count beats. flopenr #(4) BeatCountReg(.clk(HCLK), - .reset(~HRESETn | CntReset), + .reset(~HRESETn | CntReset | FinalBeat), .en(BeatCntEn), .d(NextBeatCount), .q(BeatCount)); @@ -189,6 +189,9 @@ module ahbmultimanager // basic arb always selects LSU when both // replace this block for more sophisticated arbitration. // Manager 0 (IFU) + // this logic is all wrong. + // test by removing burst. + // 2nd want to test with slower memory. assign save[0] = CurrState == IDLE & both; assign restore[0] = CurrState == ARBITRATE; assign dis[0] = CurrState == ARBITRATE; diff --git a/pipelined/src/ebu/buscachefsm.sv b/pipelined/src/ebu/buscachefsm.sv index aa261f45..09be56e0 100644 --- a/pipelined/src/ebu/buscachefsm.sv +++ b/pipelined/src/ebu/buscachefsm.sv @@ -136,10 +136,12 @@ module buscachefsm #(parameter integer WordCountThreshold, // AHB bus interface assign HTRANS = (CurrState == ADR_PHASE & HREADY & (|RW | |CacheRW)) | (CurrState == DATA_PHASE & ~HREADY) ? AHB_NONSEQ : - (CacheAccess & |WordCount) ? AHB_SEQ : AHB_IDLE; - +// (CacheAccess & |WordCount) ? AHB_SEQ : AHB_IDLE; + (CacheAccess & |WordCount) ? AHB_NONSEQ : AHB_IDLE; assign HWRITE = RW[0] | CacheRW[0]; - assign HBURST = (|CacheRW) ? LocalBurstType : 3'b0; +// assign HBURST = (|CacheRW) ? LocalBurstType : 3'b0; + // try disabling burst as it is not working with the fpga. + assign HBURST = 3'b0; always_comb begin case(WordCountThreshold)