diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do
index a4a54f90..3860decf 100644
--- a/wally-pipelined/regression/wave.do
+++ b/wally-pipelined/regression/wave.do
@@ -255,10 +255,12 @@ add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/
 add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/LRUIn
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/WayIn
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/NewLRUEn
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/LRUEn
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/LRUMask
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/LRUOut
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group replacement /testbench/dut/hart/lsu/dcache/genblk2/cacheLRU/VictimWay
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/hart/lsu/dcache/ReplacementBits
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/hart/lsu/dcache/NewReplacement
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/hart/lsu/dcache/LRUWriteEn
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable}
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid}
@@ -331,12 +333,10 @@ add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/g
 add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss
 add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit
 add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress
-add wave -noupdate -expand -group lsu -group dtlb -label {Virtual Address} /testbench/dut/hart/lsu/dmmu/Address
 add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/TLBPageFault
 add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/LoadAccessFaultM
 add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/StoreAccessFaultM
 add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBPAdr
-add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/Address
 add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/PTE
 add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBWrite
 add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/PhysicalAddress
@@ -352,80 +352,12 @@ add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu
 add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM
 add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM
 add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/hptw/genblk1/WalkerState
-add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HCLK
-add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HSELPLIC
-add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HADDR
-add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HWRITE
-add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HREADY
-add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HTRANS
-add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HWDATA
-add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/UARTIntr
-add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/GPIOIntr
-add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HREADPLIC
-add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HRESPPLIC
-add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HREADYPLIC
-add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/ExtIntM
-add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HCLK
-add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HSELGPIO
-add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HADDR
-add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HWDATA
-add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HWRITE
-add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADY
-add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HTRANS
-add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADGPIO
-add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HRESPGPIO
-add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADYGPIO
-add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsIn
-add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsOut
-add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsEn
-add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOIntr
-add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HCLK
-add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HSELCLINT
-add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HADDR
-add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HWRITE
-add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HWDATA
-add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADY
-add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HTRANS
-add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADCLINT
-add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HRESPCLINT
-add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HREADYCLINT
-add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIME
-add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/MTIMECMP
-add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/TimerIntM
-add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/SwIntM
 add wave -noupdate -group csr /testbench/dut/hart/priv/csr/MIP_REGW
-add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HCLK
-add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HRESETn
-add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HSELUART
-add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HADDR
-add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HWRITE
-add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HWDATA
-add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HREADUART
-add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HRESPUART
-add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/HREADYUART
-add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/SIN
-add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/DSRb
-add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/DCDb
-add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/CTSb
-add wave -noupdate -group uart /testbench/dut/uncore/genblk4/uart/RIb
-add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/SOUT
-add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/RTSb
-add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/DTRb
-add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/OUT1b
-add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/OUT2b
-add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/INTR
-add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/TXRDYb
-add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/genblk4/uart/RXRDYb
 add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
 add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/ITLBMissF
 add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
-add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HCLK
-add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HSELUART
-add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HADDR
-add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HWRITE
-add wave -noupdate -group UART /testbench/dut/uncore/genblk4/uart/HWDATA
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Walk read is wrong} {26824 ns} 1} {{page table setup} {8167 ns} 1} {{eviction at wrong adr} {10128 ns} 1} {{Cursor 6} {9967 ns} 0}
+WaveRestoreCursors {{Walk read is wrong} {26824 ns} 1} {{page table setup} {8167 ns} 1} {{eviction at wrong adr} {10128 ns} 1} {{Cursor 6} {7778 ns} 0}
 quietly wave cursor active 4
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 297
@@ -441,4 +373,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {9904 ns} {10352 ns}
+WaveRestoreZoom {7636 ns} {7946 ns}
diff --git a/wally-pipelined/src/cache/cacheLRU.sv b/wally-pipelined/src/cache/cacheLRU.sv
index 34fb4a82..8228e50d 100644
--- a/wally-pipelined/src/cache/cacheLRU.sv
+++ b/wally-pipelined/src/cache/cacheLRU.sv
@@ -62,7 +62,7 @@ module cacheLRU
       assign LRUMask[2] = WayIn[3] | WayIn[2];
 
       for(index = 0; index < NUMWAYS-1; index++)
-	assign LRUOut[index] = LRUEn[index] ? LRUIn[index] : LRUMask[index];
+	assign LRUOut[index] = LRUEn[index] ? LRUMask[index] : LRUIn[index];
 
       assign EncVicWay[1] = LRUIn[2];
       assign EncVicWay[0] = LRUIn[2] ? LRUIn[0] : LRUIn[1];
@@ -73,6 +73,37 @@ module cacheLRU
 
     end else if (NUMWAYS == 8) begin : EightWay
 
+      // selects
+      assign LRUEn[6] = 1'b1;
+      assign LRUEn[5] = WayIn[7] | WayIn[6] | WayIn[5] | WayIn[4];
+      assign LRUEn[4] = WayIn[7] | WayIn[6];
+      assign LRUEn[3] = WayIn[5] | WayIn[4];
+      assign LRUEn[2] = WayIn[3] | WayIn[2] | WayIn[1] | WayIn[0];
+      assign LRUEn[1] = WayIn[3] | WayIn[2];
+      assign LRUEn[0] = WayIn[1] | WayIn[0];
+
+      // mask
+      assign LRUMask[6] = WayIn[7] | WayIn[6] | WayIn[5] | WayIn[4];
+      assign LRUMask[5] = WayIn[7] | WayIn[6];
+      assign LRUMask[4] = WayIn[7];
+      assign LRUMask[3] = WayIn[5];
+      assign LRUMask[2] = WayIn[3] | WayIn[2];
+      assign LRUMask[1] = WayIn[2];
+      assign LRUMask[0] = WayIn[0];
+
+      for(index = 0; index < NUMWAYS-1; index++)
+	assign LRUOut[index] = LRUEn[index] ? LRUMask[index] : LRUIn[index];
+
+      assign EncVicWay[2] = LRUIn[6];
+      assign EncVicWay[1] = LRUIn[6] ? LRUIn[5] : LRUIn[2];
+      assign EncVicWay[0] = LRUIn[6] ? LRUIn[5] ? LRUIn[4] : LRUIn[3] :
+			    LRUIn[2] ? LRUIn[1] : LRUIn[0];
+      
+
+      oneHotDecoder #(3) 
+      oneHotDecoder(.bin(EncVicWay),
+		    .decoded({VictimWay[0], VictimWay[1], VictimWay[2], VictimWay[3],
+			      VictimWay[4], VictimWay[5], VictimWay[6], VictimWay[7]}));
     end
   endgenerate