From 2457448e297223485b1468ceabb6ebe064ef13e3 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 15 Dec 2022 08:23:34 -0800 Subject: [PATCH] Renamed DIV_BITSPERCYCLE to IDIV_BITSPERCYCLE --- pipelined/config/buildroot/wally-config.vh | 4 ++-- pipelined/config/fpga/wally-config.vh | 4 ++-- pipelined/config/rv32e/wally-config.vh | 4 ++-- pipelined/config/rv32gc/wally-config.vh | 4 ++-- pipelined/config/rv32i/wally-config.vh | 4 ++-- pipelined/config/rv32ic/wally-config.vh | 4 ++-- pipelined/config/rv64BP/wally-config.vh | 4 ++-- pipelined/config/rv64fpquad/wally-config.vh | 4 ++-- pipelined/config/rv64gc/wally-config.vh | 4 ++-- pipelined/config/rv64i/wally-config.vh | 4 ++-- pipelined/src/muldiv/intdivrestoring.sv | 12 ++++++------ pipelined/testbench/testbench.sv | 3 ++- 12 files changed, 28 insertions(+), 27 deletions(-) diff --git a/pipelined/config/buildroot/wally-config.vh b/pipelined/config/buildroot/wally-config.vh index 6b549035..52881d2b 100644 --- a/pipelined/config/buildroot/wally-config.vh +++ b/pipelined/config/buildroot/wally-config.vh @@ -70,8 +70,8 @@ `define ICACHE_LINELENINBITS 512 // Integer Divider Configuration -// DIV_BITSPERCYCLE must be 1, 2, or 4 -`define DIV_BITSPERCYCLE 4 +// IDIV_BITSPERCYCLE must be 1, 2, or 4 +`define IDIV_BITSPERCYCLE 4 `define IDIV_ON_FPU 0 // Legal number of PMP entries are 0, 16, or 64 diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh index 97b43c5b..2809961b 100644 --- a/pipelined/config/fpga/wally-config.vh +++ b/pipelined/config/fpga/wally-config.vh @@ -72,8 +72,8 @@ `define ICACHE_LINELENINBITS 512 // Integer Divider Configuration -// DIV_BITSPERCYCLE must be 1, 2, or 4 -`define DIV_BITSPERCYCLE 4 +// IDIV_BITSPERCYCLE must be 1, 2, or 4 +`define IDIV_BITSPERCYCLE 4 `define IDIV_ON_FPU 0 // Legal number of PMP entries are 0, 16, or 64 diff --git a/pipelined/config/rv32e/wally-config.vh b/pipelined/config/rv32e/wally-config.vh index 99f61c12..e9e0113b 100644 --- a/pipelined/config/rv32e/wally-config.vh +++ b/pipelined/config/rv32e/wally-config.vh @@ -71,8 +71,8 @@ `define ICACHE_LINELENINBITS 512 // Integer Divider Configuration -// DIV_BITSPERCYCLE must be 1, 2, or 4 -`define DIV_BITSPERCYCLE 1 +// IDIV_BITSPERCYCLE must be 1, 2, or 4 +`define IDIV_BITSPERCYCLE 1 `define IDIV_ON_FPU 0 // Legal number of PMP entries are 0, 16, or 64 diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh index bafe35e6..d7313ec4 100644 --- a/pipelined/config/rv32gc/wally-config.vh +++ b/pipelined/config/rv32gc/wally-config.vh @@ -70,8 +70,8 @@ `define ICACHE_LINELENINBITS 512 // Integer Divider Configuration -// DIV_BITSPERCYCLE must be 1, 2, or 4 -`define DIV_BITSPERCYCLE 4 +// IDIV_BITSPERCYCLE must be 1, 2, or 4 +`define IDIV_BITSPERCYCLE 4 `define IDIV_ON_FPU 0 // Legal number of PMP entries are 0, 16, or 64 diff --git a/pipelined/config/rv32i/wally-config.vh b/pipelined/config/rv32i/wally-config.vh index 46e493cb..77a46208 100644 --- a/pipelined/config/rv32i/wally-config.vh +++ b/pipelined/config/rv32i/wally-config.vh @@ -71,8 +71,8 @@ `define ICACHE_LINELENINBITS 512 // Integer Divider Configuration -// DIV_BITSPERCYCLE must be 1, 2, or 4 -`define DIV_BITSPERCYCLE 4 +// IDIV_BITSPERCYCLE must be 1, 2, or 4 +`define IDIV_BITSPERCYCLE 4 `define IDIV_ON_FPU 0 // Legal number of PMP entries are 0, 16, or 64 diff --git a/pipelined/config/rv32ic/wally-config.vh b/pipelined/config/rv32ic/wally-config.vh index d6ca045e..c85f3a9c 100644 --- a/pipelined/config/rv32ic/wally-config.vh +++ b/pipelined/config/rv32ic/wally-config.vh @@ -70,8 +70,8 @@ `define ICACHE_LINELENINBITS 512 // Integer Divider Configuration -// DIV_BITSPERCYCLE must be 1, 2, or 4 -`define DIV_BITSPERCYCLE 4 +// IDIV_BITSPERCYCLE must be 1, 2, or 4 +`define IDIV_BITSPERCYCLE 4 `define IDIV_ON_FPU 0 // Legal number of PMP entries are 0, 16, or 64 diff --git a/pipelined/config/rv64BP/wally-config.vh b/pipelined/config/rv64BP/wally-config.vh index 85456e2c..a67ee532 100644 --- a/pipelined/config/rv64BP/wally-config.vh +++ b/pipelined/config/rv64BP/wally-config.vh @@ -74,8 +74,8 @@ // Legal number of PMP entries are 0, 16, or 64 `define PMP_ENTRIES 64 // Integer Divider Configuration -// DIV_BITSPERCYCLE must be 1, 2, or 4 -`define DIV_BITSPERCYCLE 4 +// IDIV_BITSPERCYCLE must be 1, 2, or 4 +`define IDIV_BITSPERCYCLE 4 `define IDIV_ON_FPU 0 // Address space diff --git a/pipelined/config/rv64fpquad/wally-config.vh b/pipelined/config/rv64fpquad/wally-config.vh index eeba5699..44b8efca 100644 --- a/pipelined/config/rv64fpquad/wally-config.vh +++ b/pipelined/config/rv64fpquad/wally-config.vh @@ -72,8 +72,8 @@ `define ICACHE_LINELENINBITS 512 // Integer Divider Configuration -// DIV_BITSPERCYCLE must be 1, 2, or 4 -`define DIV_BITSPERCYCLE 4 +// IDIV_BITSPERCYCLE must be 1, 2, or 4 +`define IDIV_BITSPERCYCLE 4 `define IDIV_ON_FPU 0 // Legal number of PMP entries are 0, 16, or 64 diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh index a469a255..8e3ec34d 100644 --- a/pipelined/config/rv64gc/wally-config.vh +++ b/pipelined/config/rv64gc/wally-config.vh @@ -72,8 +72,8 @@ `define ICACHE_LINELENINBITS 512 // Integer Divider Configuration -// DIV_BITSPERCYCLE must be 1, 2, or 4 -`define DIV_BITSPERCYCLE 4 +// IDIV_BITSPERCYCLE must be 1, 2, or 4 +`define IDIV_BITSPERCYCLE 4 `define IDIV_ON_FPU 0 // Legal number of PMP entries are 0, 16, or 64 diff --git a/pipelined/config/rv64i/wally-config.vh b/pipelined/config/rv64i/wally-config.vh index 5c34b96a..bac0c7ca 100644 --- a/pipelined/config/rv64i/wally-config.vh +++ b/pipelined/config/rv64i/wally-config.vh @@ -72,8 +72,8 @@ `define ICACHE_LINELENINBITS 512 // Integer Divider Configuration -// DIV_BITSPERCYCLE must be 1, 2, or 4 -`define DIV_BITSPERCYCLE 4 +// IDIV_BITSPERCYCLE must be 1, 2, or 4 +`define IDIV_BITSPERCYCLE 4 `define IDIV_ON_FPU 0 // Legal number of PMP entries are 0, 16, or 64 diff --git a/pipelined/src/muldiv/intdivrestoring.sv b/pipelined/src/muldiv/intdivrestoring.sv index 2c7286e8..b56bb477 100644 --- a/pipelined/src/muldiv/intdivrestoring.sv +++ b/pipelined/src/muldiv/intdivrestoring.sv @@ -48,10 +48,10 @@ module intdivrestoring ( typedef enum logic [1:0] {IDLE, BUSY, DONE} statetype; statetype state; - logic [`XLEN-1:0] W[`DIV_BITSPERCYCLE:0]; - logic [`XLEN-1:0] XQ[`DIV_BITSPERCYCLE:0]; + logic [`XLEN-1:0] W[`IDIV_BITSPERCYCLE:0]; + logic [`XLEN-1:0] XQ[`IDIV_BITSPERCYCLE:0]; logic [`XLEN-1:0] DinE, XinE, DnE, DAbsBE, DAbsB, XnE, XInitE, WnM, XQnM; - localparam STEPBITS = $clog2(`XLEN/`DIV_BITSPERCYCLE); + localparam STEPBITS = $clog2(`XLEN/`IDIV_BITSPERCYCLE); logic [STEPBITS:0] step; logic Div0E, Div0M; logic DivStartE, SignXE, SignDE, NegQE, NegWM, NegQM; @@ -91,8 +91,8 @@ module intdivrestoring ( ////////////////////////////// // initialization multiplexers on first cycle of operation - mux2 #(`XLEN) wmux(W[`DIV_BITSPERCYCLE], {`XLEN{1'b0}}, DivStartE, WNext); - mux2 #(`XLEN) xmux(XQ[`DIV_BITSPERCYCLE], XInitE, DivStartE, XQNext); + mux2 #(`XLEN) wmux(W[`IDIV_BITSPERCYCLE], {`XLEN{1'b0}}, DivStartE, WNext); + mux2 #(`XLEN) xmux(XQ[`IDIV_BITSPERCYCLE], XInitE, DivStartE, XQNext); // registers before division steps flopen #(`XLEN) wreg(clk, DivBusyE, WNext, W[0]); @@ -101,7 +101,7 @@ module intdivrestoring ( // one copy of divstep for each bit produced per cycle genvar i; - for (i=0; i<`DIV_BITSPERCYCLE; i = i+1) + for (i=0; i<`IDIV_BITSPERCYCLE; i = i+1) intdivrestoringstep divstep(W[i], XQ[i], DAbsB, W[i+1], XQ[i+1]); ////////////////////////////// diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index e2edcd8b..2fe2212d 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -434,7 +434,7 @@ module riscvassertions; initial begin assert (`PMP_ENTRIES == 0 | `PMP_ENTRIES==16 | `PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64"); assert (`S_SUPPORTED | `VIRTMEM_SUPPORTED == 0) else $error("Virtual memory requires S mode support"); - assert (`DIV_BITSPERCYCLE == 1 | `DIV_BITSPERCYCLE==2 | `DIV_BITSPERCYCLE==4) else $error("Illegal number of divider bits/cycle: DIV_BITSPERCYCLE must be 1, 2, or 4"); + assert (`IDIV_BITSPERCYCLE == 1 | `IDIV_BITSPERCYCLE==2 | `IDIV_BITSPERCYCLE==4) else $error("Illegal number of divider bits/cycle: IDIV_BITSPERCYCLE must be 1, 2, or 4"); assert (`F_SUPPORTED | ~`D_SUPPORTED) else $error("Can't support double fp (D) without supporting float (F)"); assert (`D_SUPPORTED | ~`Q_SUPPORTED) else $error("Can't support quad fp (Q) without supporting double (D)"); assert (`F_SUPPORTED | ~`ZFH_SUPPORTED) else $error("Can't support half-precision fp (ZFH) without supporting float (F)"); @@ -463,6 +463,7 @@ module riscvassertions; assert ((`DCACHE == 0 & `ICACHE == 0) | `BUS) else $error("Dcache and Icache requires DBUS."); assert (`DCACHE_LINELENINBITS <= `XLEN*16 | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1"); assert (`DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words"); + assert (`IDIV_ON_FPU == 0 | `F_SUPPORTED) else $error("IDIV on FPU needs F_SUPPORTED"); end // *** DH 8/23/