diff --git a/wally-pipelined/config/buildroot/wally-config.vh b/wally-pipelined/config/buildroot/wally-config.vh
index 2224a448..c6f67880 100644
--- a/wally-pipelined/config/buildroot/wally-config.vh
+++ b/wally-pipelined/config/buildroot/wally-config.vh
@@ -90,9 +90,6 @@
 // Tie GPIO outputs back to inputs
 `define GPIO_LOOPBACK_TEST 0
 
-// Busybear special CSR config to match OVPSim
-`define OVPSIM_CSR_CONFIG 0
-
 // Hardware configuration
 `define UART_PRESCALE 1
 
diff --git a/wally-pipelined/config/busybear/wally-config.vh b/wally-pipelined/config/busybear/wally-config.vh
index 516ebcae..0db13778 100644
--- a/wally-pipelined/config/busybear/wally-config.vh
+++ b/wally-pipelined/config/busybear/wally-config.vh
@@ -91,9 +91,6 @@
 // Tie GPIO outputs back to inputs
 `define GPIO_LOOPBACK_TEST 0
 
-// Busybear special CSR config to match OVPSim
-`define OVPSIM_CSR_CONFIG 1
-
 // Hardware configuration
 //`define UART_PRESCALE 1
 `define UART_PRESCALE 0
diff --git a/wally-pipelined/config/coremark/wally-config.vh b/wally-pipelined/config/coremark/wally-config.vh
index 13d364dd..ccf0a64b 100644
--- a/wally-pipelined/config/coremark/wally-config.vh
+++ b/wally-pipelined/config/coremark/wally-config.vh
@@ -88,9 +88,6 @@
 // Tie GPIO outputs back to inputs
 `define GPIO_LOOPBACK_TEST 0
 
-// Busybear special CSR config to match OVPSim
-`define OVPSIM_CSR_CONFIG 0
-
 // Hardware configuration
 `define UART_PRESCALE 1
 
diff --git a/wally-pipelined/config/coremark_bare/wally-config.vh b/wally-pipelined/config/coremark_bare/wally-config.vh
index 828dd084..d55200b4 100644
--- a/wally-pipelined/config/coremark_bare/wally-config.vh
+++ b/wally-pipelined/config/coremark_bare/wally-config.vh
@@ -91,9 +91,6 @@
 // Tie GPIO outputs back to inputs
 `define GPIO_LOOPBACK_TEST 1
 
-// Busybear special CSR config to match OVPSim
-`define OVPSIM_CSR_CONFIG 0
-
 // Hardware configuration
 `define UART_PRESCALE 1
 
diff --git a/wally-pipelined/config/rv32ic/wally-config.vh b/wally-pipelined/config/rv32ic/wally-config.vh
index f6f1860a..b6878061 100644
--- a/wally-pipelined/config/rv32ic/wally-config.vh
+++ b/wally-pipelined/config/rv32ic/wally-config.vh
@@ -90,9 +90,6 @@
 // Tie GPIO outputs back to inputs
 `define GPIO_LOOPBACK_TEST 1
 
-// Busybear special CSR config to match OVPSim
-`define OVPSIM_CSR_CONFIG 0
-
 // Hardware configuration
 `define UART_PRESCALE 1
 
diff --git a/wally-pipelined/config/rv64BP/wally-config.vh b/wally-pipelined/config/rv64BP/wally-config.vh
index 477055de..2e5eaf37 100644
--- a/wally-pipelined/config/rv64BP/wally-config.vh
+++ b/wally-pipelined/config/rv64BP/wally-config.vh
@@ -89,9 +89,6 @@
 // Tie GPIO outputs back to inputs
 `define GPIO_LOOPBACK_TEST 1
 
-// Busybear special CSR config to match OVPSim
-`define OVPSIM_CSR_CONFIG 0
-
 // Hardware configuration
 `define UART_PRESCALE 1
 
diff --git a/wally-pipelined/config/rv64ic/wally-config.vh b/wally-pipelined/config/rv64ic/wally-config.vh
index 32943165..954e126b 100644
--- a/wally-pipelined/config/rv64ic/wally-config.vh
+++ b/wally-pipelined/config/rv64ic/wally-config.vh
@@ -91,9 +91,6 @@
 // Tie GPIO outputs back to inputs
 `define GPIO_LOOPBACK_TEST 1
 
-// Busybear special CSR config to match OVPSim
-`define OVPSIM_CSR_CONFIG 0
-
 // Hardware configuration
 `define UART_PRESCALE 1
 
diff --git a/wally-pipelined/config/rv64icfd/wally-config.vh b/wally-pipelined/config/rv64icfd/wally-config.vh
index e5ccc0bf..29322210 100644
--- a/wally-pipelined/config/rv64icfd/wally-config.vh
+++ b/wally-pipelined/config/rv64icfd/wally-config.vh
@@ -91,9 +91,6 @@
 // Tie GPIO outputs back to inputs
 `define GPIO_LOOPBACK_TEST 1
 
-// Busybear special CSR config to match OVPSim
-`define OVPSIM_CSR_CONFIG 0
-
 // Hardware configuration
 `define UART_PRESCALE 1
 
diff --git a/wally-pipelined/config/rv64imc/wally-config.vh b/wally-pipelined/config/rv64imc/wally-config.vh
index b6f5ab9a..5ecb9bef 100644
--- a/wally-pipelined/config/rv64imc/wally-config.vh
+++ b/wally-pipelined/config/rv64imc/wally-config.vh
@@ -87,9 +87,6 @@
 // Tie GPIO outputs back to inputs
 `define GPIO_LOOPBACK_TEST 0
 
-// Busybear special CSR config to match OVPSim
-`define OVPSIM_CSR_CONFIG 0
-
 // Hardware configuration
 `define UART_PRESCALE 1
 
diff --git a/wally-pipelined/src/privileged/csrm.sv b/wally-pipelined/src/privileged/csrm.sv
index 0190a4e1..61128074 100644
--- a/wally-pipelined/src/privileged/csrm.sv
+++ b/wally-pipelined/src/privileged/csrm.sv
@@ -162,7 +162,7 @@ module csrm #(parameter
   flopenr #(`XLEN) MCAUSEreg(clk, reset, WriteMCAUSEM, NextCauseM, MCAUSE_REGW); 
   flopenr #(`XLEN) MTVALreg(clk, reset, WriteMTVALM, NextMtvalM, MTVAL_REGW);
   generate
-    if (`OVPSIM_CSR_CONFIG)
+    if (`BUSYBEAR == 1)
       flopenl #(32)   MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, {CSRWriteValM[31:2],1'b0,CSRWriteValM[0]}, 32'b0, MCOUNTEREN_REGW);
     else if (`BUILDROOT == 1)
       flopenl #(32)   MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], 32'h0, MCOUNTEREN_REGW);
diff --git a/wally-pipelined/src/privileged/csrs.sv b/wally-pipelined/src/privileged/csrs.sv
index 14e838f6..0afe7091 100644
--- a/wally-pipelined/src/privileged/csrs.sv
+++ b/wally-pipelined/src/privileged/csrs.sv
@@ -89,7 +89,7 @@ module csrs #(parameter
       flopenl #(`XLEN) SCAUSEreg(clk, reset, WriteSCAUSEM, NextCauseM, `XLEN'b0, SCAUSE_REGW); 
       flopenr #(`XLEN) STVALreg(clk, reset, WriteSTVALM, NextMtvalM, STVAL_REGW);
       flopenr #(`XLEN) SATPreg(clk, reset, WriteSATPM, CSRWriteValM, SATP_REGW);
-      if (`OVPSIM_CSR_CONFIG)
+      if (`BUSYBEAR == 1)
         flopenl #(32)   SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, {CSRWriteValM[31:2],1'b0,CSRWriteValM[0]}, 32'b0, SCOUNTEREN_REGW);
       else if (`BUILDROOT == 1)
         flopenl #(32)   SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], 32'h0, SCOUNTEREN_REGW);