From 20606837707bdbf27230ff28a55361291035503d Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 17 Feb 2023 15:15:37 -0800 Subject: [PATCH] Continue fixing memory macros for synthesis --- src/generic/mem/ram1p1rwbe_64x128.sv | 2 +- src/generic/mem/ram1p1rwbe_64x22.sv | 2 +- src/generic/mem/ram1p1rwbe_64x44.sv | 2 +- src/generic/mem/ram2p1r1wbe_1024x36.sv | 2 +- src/generic/mem/ram2p1r1wbe_1024x68.sv | 2 +- src/generic/mem/ram2p1r1wbe_64x32.sv | 2 +- synthDC/.synopsys_dc.setup | 2 +- synthDC/extractSummary.py | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/generic/mem/ram1p1rwbe_64x128.sv b/src/generic/mem/ram1p1rwbe_64x128.sv index a28b64e9..84a3e74f 100755 --- a/src/generic/mem/ram1p1rwbe_64x128.sv +++ b/src/generic/mem/ram1p1rwbe_64x128.sv @@ -36,6 +36,6 @@ module ram1p1rwbe_64x128( // replace "generic64x128RAM" with "TS1N..64X128.." module from your memory vendor //generic64x128RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q); - ts1n28hpcpsvtb64x128m4sw_180a sramIP(.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q); + TS1N28HPCPSVTB64X128M4SW sramIP(.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q); endmodule diff --git a/src/generic/mem/ram1p1rwbe_64x22.sv b/src/generic/mem/ram1p1rwbe_64x22.sv index 8b04c797..3020e0fd 100755 --- a/src/generic/mem/ram1p1rwbe_64x22.sv +++ b/src/generic/mem/ram1p1rwbe_64x22.sv @@ -36,7 +36,7 @@ module ram1p1rwbe_64x22( // replace "generic64x22RAM" with "TS1N..64X22.." module from your memory vendor // use part of a larger RAM to avoid generating more flavors of RAM - ts1n28hpcpsvtb64x44m4sw_180a sramIP(.CLK, .CEB, .WEB, .A, .D(D[21:0]), .BWEB(BWEB[21:0]), .Q(Q[21:0])); + TS1N28HPCPSVTB64X44M4SW sramIP(.CLK, .CEB, .WEB, .A, .D(D[21:0]), .BWEB(BWEB[21:0]), .Q(Q[21:0])); //generic64x22RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q); endmodule diff --git a/src/generic/mem/ram1p1rwbe_64x44.sv b/src/generic/mem/ram1p1rwbe_64x44.sv index 080dd997..89730a42 100644 --- a/src/generic/mem/ram1p1rwbe_64x44.sv +++ b/src/generic/mem/ram1p1rwbe_64x44.sv @@ -36,6 +36,6 @@ module ram1p1rwbe_64x44( // replace "generic64x44RAM" with "TS1N..64X44.." module from your memory vendor // generic64x44RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q); - ts1n28hpcpsvtb64x44m4sw_180a sramIP(.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q); + TS1N28HPCPSVTB64X44M4SW sramIP(.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q); endmodule diff --git a/src/generic/mem/ram2p1r1wbe_1024x36.sv b/src/generic/mem/ram2p1r1wbe_1024x36.sv index 7ceef23c..aee2d0aa 100755 --- a/src/generic/mem/ram2p1r1wbe_1024x36.sv +++ b/src/generic/mem/ram2p1r1wbe_1024x36.sv @@ -45,7 +45,7 @@ module ram2p1r1wbe_1024x36( //generic1024x36RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, // .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); // use part of a larger RAM to avoid generating more flavors of RAM - tsdn28hpcpa1024x68m4mw_130a sramIP(.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, + TSDN28HPCPA1024X68M4MW sramIP(.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, .AA, .AB, .DA(DA[35:0]), .DB(DB[35:0]), .BWEBA(BWEBA[35:0]), .BWEBB(BWEBB[35:0]), .QA(QA[35:0]), .QB(QB[35:0])); diff --git a/src/generic/mem/ram2p1r1wbe_1024x68.sv b/src/generic/mem/ram2p1r1wbe_1024x68.sv index c6c0f01a..108530be 100755 --- a/src/generic/mem/ram2p1r1wbe_1024x68.sv +++ b/src/generic/mem/ram2p1r1wbe_1024x68.sv @@ -44,7 +44,7 @@ module ram2p1r1wbe_1024x68( // replace "generic1024x68RAM" with "TSDN..1024X68.." module from your memory vendor //generic1024x68RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, // .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); - tsdn28hpcpa1024x68m4mw_130a sramIP(.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, + TSDN28HPCPA1024X68M4MW sramIP(.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); endmodule diff --git a/src/generic/mem/ram2p1r1wbe_64x32.sv b/src/generic/mem/ram2p1r1wbe_64x32.sv index da080b2c..c18db670 100755 --- a/src/generic/mem/ram2p1r1wbe_64x32.sv +++ b/src/generic/mem/ram2p1r1wbe_64x32.sv @@ -46,6 +46,6 @@ module ram2p1r1wbe_64x32( // .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); //generic64x32RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, // .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); - tsdn28hpcpa64x32m4mw_130a sramIP(.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, + TSDN28HPCPA64X32M4MW sramIP(.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); endmodule diff --git a/synthDC/.synopsys_dc.setup b/synthDC/.synopsys_dc.setup index 3c8b566a..c516fcf6 100755 --- a/synthDC/.synopsys_dc.setup +++ b/synthDC/.synopsys_dc.setup @@ -67,7 +67,7 @@ set cache_read $cache_write lappend search_path ./scripts lappend search_path ./hdl lappend search_path ./mapped -if {$tech == "tsmc28"} { +if {$tech == "tsmc28" || $tech == "tsmc28psyn"} { set memory /home/jstine/WallyMem/rv64gc/ lappend target_library $memory/ts3n28hpcpa128x64m8m_130a/NLDM/ts3n28hpcpa128x64m8m_tt0p9v25c.db lappend target_library $memory/ts1n28hpcpsvtb64x128m4sw_180a/NLDM/ts1n28hpcpsvtb64x128m4sw_tt0p9v25c.db diff --git a/synthDC/extractSummary.py b/synthDC/extractSummary.py index 5aeb5aa9..85bc6f0a 100755 --- a/synthDC/extractSummary.py +++ b/synthDC/extractSummary.py @@ -85,7 +85,7 @@ def freqPlot(tech, width, config): freqsL, delaysL, areasL = ([[], []] for i in range(3)) for oneSynth in allSynths: if (width == oneSynth.width) & (config == oneSynth.config) & (tech == oneSynth.tech) & ('orig' == oneSynth.mod): - ind = (1000/oneSynth.delay < oneSynth.freq) # when delay is within target clock period + ind = (1000/oneSynth.delay < (0.95*oneSynth.freq)) # when delay is within target clock period freqsL[ind] += [oneSynth.freq] delaysL[ind] += [oneSynth.delay] areasL[ind] += [oneSynth.area]