forked from Github_Repos/cvw
		
	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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						commit
						20546857e6
					
				@ -51,9 +51,9 @@
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`define UARCH_SINGLECYCLE 0
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					`define UARCH_SINGLECYCLE 0
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// LSU microarchitectural Features
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					// LSU microarchitectural Features
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`define BUS 1
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					`define BUS 1
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`define DCACHE 1
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					`define DCACHE 0
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`define ICACHE 1
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					`define ICACHE 0
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`define VIRTMEM_SUPPORTED 1
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					`define VIRTMEM_SUPPORTED 0
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`define VECTORED_INTERRUPTS_SUPPORTED 1 
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					`define VECTORED_INTERRUPTS_SUPPORTED 1 
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`define BIGENDIAN_SUPPORTED 0
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					`define BIGENDIAN_SUPPORTED 0
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@ -86,16 +86,16 @@
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// Peripheral Addresses
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					// Peripheral Addresses
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// Peripheral memory space extends from BASE to BASE+RANGE
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					// Peripheral memory space extends from BASE to BASE+RANGE
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// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
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					// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
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`define DTIM_SUPPORTED 1'b0
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					`define DTIM_SUPPORTED 1'b1
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`define DTIM_BASE       34'h80000000
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					`define DTIM_BASE       34'h80000000
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`define DTIM_RANGE      34'h00001FFF
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					`define DTIM_RANGE      34'h07FFFFFF
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`define IROM_SUPPORTED 1'b0
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					`define IROM_SUPPORTED 1'b1
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`define IROM_BASE       34'h80000000
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					`define IROM_BASE       34'h80000000
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`define IROM_RANGE      34'h00001FFF
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					`define IROM_RANGE      34'h07FFFFFF
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`define BOOTROM_SUPPORTED 1'b1
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					`define BOOTROM_SUPPORTED 1'b1
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`define BOOTROM_BASE   34'h00001000 
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					`define BOOTROM_BASE   34'h00001000 
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`define BOOTROM_RANGE  34'h00000FFF
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					`define BOOTROM_RANGE  34'h00000FFF
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`define UNCORE_RAM_SUPPORTED 1'b1
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					`define UNCORE_RAM_SUPPORTED 1'b0
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`define UNCORE_RAM_BASE       34'h80000000
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					`define UNCORE_RAM_BASE       34'h80000000
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`define UNCORE_RAM_RANGE      34'h07FFFFFF
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					`define UNCORE_RAM_RANGE      34'h07FFFFFF
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`define EXT_MEM_SUPPORTED 1'b0
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					`define EXT_MEM_SUPPORTED 1'b0
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