forked from Github_Repos/cvw
Removed EarlyTermShift from fdiv
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a36747fda0
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1e6bd26bb6
@ -4,7 +4,6 @@ module divshiftcalc(
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input logic [`DIVb-(`RADIX/4):0] DivQm,
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input logic [`DIVb-(`RADIX/4):0] DivQm,
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input logic [`FMTBITS-1:0] Fmt,
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input logic [`FMTBITS-1:0] Fmt,
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input logic Sqrt,
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input logic Sqrt,
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input logic [`DURLEN-1:0] DivEarlyTermShift,
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input logic [`NE+1:0] DivQe,
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input logic [`NE+1:0] DivQe,
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output logic [$clog2(`NORMSHIFTSZ)-1:0] DivShiftAmt,
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output logic [$clog2(`NORMSHIFTSZ)-1:0] DivShiftAmt,
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output logic [`NORMSHIFTSZ-1:0] DivShiftIn,
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output logic [`NORMSHIFTSZ-1:0] DivShiftIn,
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@ -13,6 +12,8 @@ module divshiftcalc(
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);
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);
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logic [`NE+1:0] NormShift;
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logic [`NE+1:0] NormShift;
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logic [`DURLEN-1:0] DivEarlyTermShift = 0;
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// is the result denromalized
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// is the result denromalized
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// if the exponent is 1 then the result needs to be normalized then the result is denormalizes
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// if the exponent is 1 then the result needs to be normalized then the result is denormalizes
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assign DivResDenorm = DivQe[`NE+1]|(~|DivQe[`NE+1:0]);
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assign DivResDenorm = DivQe[`NE+1]|(~|DivQe[`NE+1:0]);
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@ -35,7 +36,8 @@ module divshiftcalc(
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assign NormShift = (`NE+2)'(`NF);
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assign NormShift = (`NE+2)'(`NF);
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// if the shift amount is negitive then dont shift (keep sticky bit)
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// if the shift amount is negitive then dont shift (keep sticky bit)
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// need to multiply the early termination shift by LOGR*DIVCOPIES = left shift of log2(LOGR*DIVCOPIES)
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// need to multiply the early termination shift by LOGR*DIVCOPIES = left shift of log2(LOGR*DIVCOPIES)
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assign DivShiftAmt = (DivResDenorm ? DivDenormShift[$clog2(`NORMSHIFTSZ)-1:0]&{$clog2(`NORMSHIFTSZ){~DivDenormShift[`NE+1]}} : NormShift[$clog2(`NORMSHIFTSZ)-1:0])+{{$clog2(`NORMSHIFTSZ)-`DURLEN-$clog2(`LOGR*`DIVCOPIES){1'b0}}, DivEarlyTermShift&{`DURLEN{~(DivDenormShift[`NE+1]|Sqrt)}}, {$clog2(`LOGR*`DIVCOPIES){1'b0}}};
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assign DivShiftAmt = (DivResDenorm ? DivDenormShift[$clog2(`NORMSHIFTSZ)-1:0]&{$clog2(`NORMSHIFTSZ){~DivDenormShift[`NE+1]}} : NormShift[$clog2(`NORMSHIFTSZ)-1:0])+{{$clog2(`NORMSHIFTSZ)-`DURLEN-$clog2(`LOGR*`DIVCOPIES){1'b0}},
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DivEarlyTermShift&{`DURLEN{~(DivDenormShift[`NE+1]|Sqrt)}}, {$clog2(`LOGR*`DIVCOPIES){1'b0}}};
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assign DivShiftIn = {{`NF{1'b0}}, DivQm, {`NORMSHIFTSZ-`DIVb+1+(`RADIX/4)-`NF{1'b0}}};
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assign DivShiftIn = {{`NF{1'b0}}, DivQm, {`NORMSHIFTSZ-`DIVb+1+(`RADIX/4)-`NF{1'b0}}};
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@ -48,7 +48,6 @@ module fdivsqrt(
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output logic DivBusy,
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output logic DivBusy,
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output logic DivDone,
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output logic DivDone,
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output logic [`NE+1:0] QeM,
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output logic [`NE+1:0] QeM,
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output logic [`DURLEN-1:0] EarlyTermShiftM,
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output logic [`DIVb-(`RADIX/4):0] QmM
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output logic [`DIVb-(`RADIX/4):0] QmM
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// output logic [`XLEN-1:0] RemM,
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// output logic [`XLEN-1:0] RemM,
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);
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);
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@ -70,7 +69,7 @@ module fdivsqrt(
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.clk, .reset, .FmtE, .XsE, .SqrtE,
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.clk, .reset, .FmtE, .XsE, .SqrtE,
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.DivBusy, .DivStart(DivStartE),.StallE, .StallM, .DivDone, .XZeroE, .YZeroE,
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.DivBusy, .DivStart(DivStartE),.StallE, .StallM, .DivDone, .XZeroE, .YZeroE,
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.XNaNE, .YNaNE,
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.XNaNE, .YNaNE,
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.XInfE, .YInfE, .EarlyTermShiftE(EarlyTermShiftM), .WZero);
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.XInfE, .YInfE, .WZero);
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fdivsqrtiter fdivsqrtiter(
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fdivsqrtiter fdivsqrtiter(
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.clk, .Firstqn, .D, .FirstU, .FirstUM, .FirstC, .SqrtE, .SqrtM,
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.clk, .Firstqn, .D, .FirstU, .FirstUM, .FirstC, .SqrtE, .SqrtM,
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.X,.Dpreproc, .FirstWS(WS), .FirstWC(WC), .NextWSN, .NextWCN,
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.X,.Dpreproc, .FirstWS(WS), .FirstWC(WC), .NextWSN, .NextWCN,
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@ -43,7 +43,6 @@ module fdivsqrtfsm(
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input logic StallE,
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input logic StallE,
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input logic StallM,
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input logic StallM,
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input logic WZero,
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input logic WZero,
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output logic [`DURLEN-1:0] EarlyTermShiftE,
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output logic DivDone,
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output logic DivDone,
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output logic DivBusy
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output logic DivBusy
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);
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);
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@ -55,9 +54,6 @@ module fdivsqrtfsm(
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logic SpecialCase;
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logic SpecialCase;
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logic [`DURLEN-1:0] cycles;
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logic [`DURLEN-1:0] cycles;
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assign EarlyTermShiftE = 0; // *** remove this signal when having unified design
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// assign EarlyTermShiftE = step;
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// terminate immediately on special cases
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// terminate immediately on special cases
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assign SpecialCase = XZeroE | (YZeroE&~SqrtE) | XInfE | YInfE | XNaNE | YNaNE | (XsE&SqrtE);
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assign SpecialCase = XZeroE | (YZeroE&~SqrtE) | XInfE | YInfE | XNaNE | YNaNE | (XsE&SqrtE);
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@ -44,9 +44,9 @@ module fdivsqrtpostproc(
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logic [`DIVb+3:0] W;
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logic [`DIVb+3:0] W;
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logic NegSticky;
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logic NegSticky;
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logic weq0;
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// check for early termination on an exact result. If the result is not exact, the sticky should be set
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// check for early termination on an exact result. If the result is not exact, the sticky should be set
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logic weq0;
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aplusbeq0 #(`DIVb+4) wspluswceq0(WS, WC, weq0);
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aplusbeq0 #(`DIVb+4) wspluswceq0(WS, WC, weq0);
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if (`RADIX == 2) begin
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if (`RADIX == 2) begin
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@ -73,11 +73,4 @@ module fdivsqrtpostproc(
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always_comb
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always_comb
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if(NegSticky) QmM = FirstUM[`DIVb-(`RADIX/4):0] << SqrtM;
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if(NegSticky) QmM = FirstUM[`DIVb-(`RADIX/4):0] << SqrtM;
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else QmM = FirstU[`DIVb-(`RADIX/4):0] << SqrtM;
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else QmM = FirstU[`DIVb-(`RADIX/4):0] << SqrtM;
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/* if(SqrtM) // sqrt ouputs in the range (1, .5]
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if(NegSticky) QmM = {FirstUM[`DIVb-1-(`RADIX/4):0], 1'b0};
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else QmM = {FirstU[`DIVb-1-(`RADIX/4):0], 1'b0};
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else
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if(NegSticky) QmM = FirstUM[`DIVb-(`RADIX/4):0];
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else QmM = FirstU[`DIVb-(`RADIX/4):0]; */
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endmodule
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endmodule
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@ -127,7 +127,6 @@ module fpu (
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logic [`NE+1:0] QeE, QeM;
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logic [`NE+1:0] QeE, QeM;
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logic DivSE, DivSM;
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logic DivSE, DivSM;
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logic DivDoneM;
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logic DivDoneM;
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logic [`DURLEN-1:0] EarlyTermShiftM;
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// result and flag signals
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// result and flag signals
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logic [`XLEN-1:0] ClassResE; // classify result
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logic [`XLEN-1:0] ClassResE; // classify result
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@ -260,7 +259,7 @@ module fpu (
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fdivsqrt fdivsqrt(.clk, .reset, .FmtE, .XmE, .YmE, .XeE, .YeE, .SqrtE(OpCtrlE[0]), .SqrtM(OpCtrlM[0]),
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fdivsqrt fdivsqrt(.clk, .reset, .FmtE, .XmE, .YmE, .XeE, .YeE, .SqrtE(OpCtrlE[0]), .SqrtM(OpCtrlM[0]),
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.XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .DivStartE(DivStartE), .XsE,
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.XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .DivStartE(DivStartE), .XsE,
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.StallE, .StallM, .DivSM, .DivBusy(FDivBusyE), .QeM, //***change divbusyE to M signal
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.StallE, .StallM, .DivSM, .DivBusy(FDivBusyE), .QeM, //***change divbusyE to M signal
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.EarlyTermShiftM, .QmM, .DivDone(DivDoneM));
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.QmM, .DivDone(DivDoneM));
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// compare
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// compare
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// - fmin/fmax
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// - fmin/fmax
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// - flt/fle/feq
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// - flt/fle/feq
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@ -364,7 +363,7 @@ module fpu (
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assign FpLoadStoreM = FResSelM[1];
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assign FpLoadStoreM = FResSelM[1];
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postprocess postprocess(.Xs(XsM), .Ys(YsM), .Ze(ZeM), .Xm(XmM), .Ym(YmM), .Zm(ZmM), .Frm(FrmM), .Fmt(FmtM), .FmaPe(PeM), .DivEarlyTermShift(EarlyTermShiftM),
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postprocess postprocess(.Xs(XsM), .Ys(YsM), .Ze(ZeM), .Xm(XmM), .Ym(YmM), .Zm(ZmM), .Frm(FrmM), .Fmt(FmtM), .FmaPe(PeM),
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.FmaZmS(ZmStickyM), .FmaKillProd(KillProdM), .XZero(XZeroM), .YZero(YZeroM), .ZZero(ZZeroM), .XInf(XInfM), .YInf(YInfM), .DivQm(QmM), .FmaSs(SsM),
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.FmaZmS(ZmStickyM), .FmaKillProd(KillProdM), .XZero(XZeroM), .YZero(YZeroM), .ZZero(ZZeroM), .XInf(XInfM), .YInf(YInfM), .DivQm(QmM), .FmaSs(SsM),
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.ZInf(ZInfM), .XNaN(XNaNM), .YNaN(YNaNM), .ZNaN(ZNaNM), .XSNaN(XSNaNM), .YSNaN(YSNaNM), .ZSNaN(ZSNaNM), .FmaSm(SmM), .DivQe(QeM), .DivDone(DivDoneM),
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.ZInf(ZInfM), .XNaN(XNaNM), .YNaN(YNaNM), .ZNaN(ZNaNM), .XSNaN(XSNaNM), .YSNaN(YSNaNM), .ZSNaN(ZSNaNM), .FmaSm(SmM), .DivQe(QeM), .DivDone(DivDoneM),
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.FmaNegSum(NegSumM), .FmaInvA(InvAM), .ZDenorm(ZDenormM), .FmaAs(AsM), .FmaPs(PsM), .OpCtrl(OpCtrlM), .FmaSCnt(SCntM), .FmaSe(SeM),
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.FmaNegSum(NegSumM), .FmaInvA(InvAM), .ZDenorm(ZDenormM), .FmaAs(AsM), .FmaPs(PsM), .OpCtrl(OpCtrlM), .FmaSCnt(SCntM), .FmaSe(SeM),
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@ -56,7 +56,6 @@ module postprocess (
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input logic FmaSs,
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input logic FmaSs,
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input logic [$clog2(3*`NF+7)-1:0] FmaSCnt, // the normalization shift count
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input logic [$clog2(3*`NF+7)-1:0] FmaSCnt, // the normalization shift count
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//divide signals
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//divide signals
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input logic [`DURLEN-1:0] DivEarlyTermShift,
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input logic DivS,
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input logic DivS,
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input logic DivDone,
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input logic DivDone,
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input logic [`NE+1:0] DivQe,
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input logic [`NE+1:0] DivQe,
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@ -152,7 +151,7 @@ module postprocess (
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.XZero, .IntToFp, .OutFmt, .CvtResUf, .CvtShiftIn);
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.XZero, .IntToFp, .OutFmt, .CvtResUf, .CvtShiftIn);
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fmashiftcalc fmashiftcalc(.FmaSm, .Ze, .FmaPe, .FmaSCnt, .Fmt, .FmaKillProd, .NormSumExp, .FmaSe,
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fmashiftcalc fmashiftcalc(.FmaSm, .Ze, .FmaPe, .FmaSCnt, .Fmt, .FmaKillProd, .NormSumExp, .FmaSe,
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.FmaSZero, .FmaPreResultDenorm, .FmaShiftAmt, .FmaShiftIn);
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.FmaSZero, .FmaPreResultDenorm, .FmaShiftAmt, .FmaShiftIn);
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divshiftcalc divshiftcalc(.Fmt, .Sqrt, .DivQe, .DivQm, .DivEarlyTermShift, .DivResDenorm, .DivDenormShift, .DivShiftAmt, .DivShiftIn);
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divshiftcalc divshiftcalc(.Fmt, .Sqrt, .DivQe, .DivQm, .DivResDenorm, .DivDenormShift, .DivShiftAmt, .DivShiftIn);
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always_comb
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always_comb
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case(PostProcSel)
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case(PostProcSel)
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@ -82,7 +82,6 @@ module testbenchfp;
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logic [`LOGCVTLEN-1:0] CvtShiftAmtE; // how much to shift by
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logic [`LOGCVTLEN-1:0] CvtShiftAmtE; // how much to shift by
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logic [`DIVb-(`RADIX/4):0] Quot;
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logic [`DIVb-(`RADIX/4):0] Quot;
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logic CvtResDenormUfE;
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logic CvtResDenormUfE;
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logic [`DURLEN-1:0] EarlyTermShift;
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logic DivStart, DivBusy;
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logic DivStart, DivBusy;
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logic reset = 1'b0;
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logic reset = 1'b0;
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logic [$clog2(`NF+2)-1:0] XZeroCnt, YZeroCnt;
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logic [$clog2(`NF+2)-1:0] XZeroCnt, YZeroCnt;
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@ -701,7 +700,7 @@ module testbenchfp;
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.XInf(XInf), .YInf(YInf), .ZInf(ZInf), .CvtCs(CvtResSgnE), .ToInt(WriteIntVal),
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.XInf(XInf), .YInf(YInf), .ZInf(ZInf), .CvtCs(CvtResSgnE), .ToInt(WriteIntVal),
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.XSNaN(XSNaN), .YSNaN(YSNaN), .ZSNaN(ZSNaN), .CvtLzcIn(CvtLzcInE), .IntZero,
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.XSNaN(XSNaN), .YSNaN(YSNaN), .ZSNaN(ZSNaN), .CvtLzcIn(CvtLzcInE), .IntZero,
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.FmaKillProd(KillProd), .FmaZmS(ZmSticky), .FmaPe(Pe), .DivDone, .FmaSe(Se),
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.FmaKillProd(KillProd), .FmaZmS(ZmSticky), .FmaPe(Pe), .DivDone, .FmaSe(Se),
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.FmaSm(Sm), .FmaNegSum(NegSum), .FmaInvA(InvA), .FmaSCnt(SCnt), .DivEarlyTermShift(EarlyTermShift), .FmaAs(As), .FmaPs(Ps), .Fmt(ModFmt), .Frm(FrmVal),
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.FmaSm(Sm), .FmaNegSum(NegSum), .FmaInvA(InvA), .FmaSCnt(SCnt), .FmaAs(As), .FmaPs(Ps), .Fmt(ModFmt), .Frm(FrmVal),
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.PostProcFlg(Flg), .PostProcRes(FpRes), .FCvtIntRes(IntRes));
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.PostProcFlg(Flg), .PostProcRes(FpRes), .FCvtIntRes(IntRes));
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if (TEST === "cvtfp" | TEST === "cvtint" | TEST === "all") begin : fcvt
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if (TEST === "cvtfp" | TEST === "cvtint" | TEST === "all") begin : fcvt
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@ -719,7 +718,7 @@ module testbenchfp;
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fdivsqrt fdivsqrt(.clk, .reset, .XsE(Xs), .FmtE(ModFmt), .XmE(Xm), .YmE(Ym), .XeE(Xe), .YeE(Ye), .SqrtE(OpCtrlVal[0]), .SqrtM(OpCtrlVal[0]),
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fdivsqrt fdivsqrt(.clk, .reset, .XsE(Xs), .FmtE(ModFmt), .XmE(Xm), .YmE(Ym), .XeE(Xe), .YeE(Ye), .SqrtE(OpCtrlVal[0]), .SqrtM(OpCtrlVal[0]),
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.XInfE(XInf), .YInfE(YInf), .XZeroE(XZero), .YZeroE(YZero), .XNaNE(XNaN), .YNaNE(YNaN), .DivStartE(DivStart),
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.XInfE(XInf), .YInfE(YInf), .XZeroE(XZero), .YZeroE(YZero), .XNaNE(XNaN), .YNaNE(YNaN), .DivStartE(DivStart),
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.StallE(1'b0), .StallM(1'b0), .DivSM(DivSticky), .DivBusy, .QeM(DivCalcExp),
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.StallE(1'b0), .StallM(1'b0), .DivSM(DivSticky), .DivBusy, .QeM(DivCalcExp),
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.EarlyTermShiftM(EarlyTermShift), .QmM(Quot), .DivDone);
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.QmM(Quot), .DivDone);
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end
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end
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assign CmpFlg[3:0] = 0;
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assign CmpFlg[3:0] = 0;
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