From 96995c559365db48ca7c3dea01fc611a111e7028 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Mar 2023 11:22:09 -0800 Subject: [PATCH 01/10] removed redundant zbs --- src/ieu/bmu/zbs.sv | 59 ---------------------------------------------- 1 file changed, 59 deletions(-) delete mode 100644 src/ieu/bmu/zbs.sv diff --git a/src/ieu/bmu/zbs.sv b/src/ieu/bmu/zbs.sv deleted file mode 100644 index 214d6e2c..00000000 --- a/src/ieu/bmu/zbs.sv +++ /dev/null @@ -1,59 +0,0 @@ -/////////////////////////////////////////// -// zbs.sv -// -// Written: Kevin Kim and Kip Macsai-Goren -// Created: 31 January 2023 -// Modified: -// -// Purpose: RISC-V single bit manipulation unit (ZBS instructions) -// -// Documentation: RISC-V System on Chip Design Chapter *** -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module zbs #(parameter WIDTH=32) ( - input logic [WIDTH-1:0] A, B, // Operands - //input logic [2:0] ALUControl, // With Funct3, indicates operation to perform - input logic [6:0] Funct7, - input logic [2:0] Funct3, // With ***Control, indicates operation to perform - output logic [WIDTH-1:0] ZBSResult); // ZBS result - - logic [WIDTH-1:0] BMask, ClrResult, InvResult, ExtResult, SetResult; - - decoder #($clog2(WIDTH)) maskgen (B[$clog2(WIDTH)-1:0], BMask); - - assign InvResult = A ^ BMask; - assign ClrResult = A & ~BMask; - assign SetResult = A | BMask; - assign ExtResult = {{(WIDTH-1){1'b0}},{|(A & BMask)}}; - - always_comb begin - casez ({Funct7, Funct3}) - 10'b010010?_001: ZBSResult = ClrResult; - 10'b010010?_101: ZBSResult = ExtResult; - 10'b011010?_001: ZBSResult = InvResult; - 10'b001010?_001: ZBSResult = SetResult; - default: ZBSResult = 0; // *** expand to include faults - endcase - end - -endmodule - From 44d40afca817b7615b104ef447b86901cb2e3464 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Mar 2023 11:36:12 -0800 Subject: [PATCH 02/10] fixed controller lint, changed byte unit mux select name and input width --- src/ieu/bmu/byte.sv | 5 +++-- src/ieu/bmu/zbb.sv | 2 +- src/ieu/controller.sv | 2 +- 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/src/ieu/bmu/byte.sv b/src/ieu/bmu/byte.sv index efd43d84..2b98b83d 100644 --- a/src/ieu/bmu/byte.sv +++ b/src/ieu/bmu/byte.sv @@ -30,7 +30,8 @@ `include "wally-config.vh" module byteUnit #(parameter WIDTH=32) ( - input logic [WIDTH-1:0] A, B, // Operands + input logic [WIDTH-1:0] A, // Operands + input logic ByteSelect, // LSB of Immediate output logic [WIDTH-1:0] ByteResult); // rev8, orcb result logic [WIDTH-1:0] OrcBResult, Rev8Result; @@ -41,6 +42,6 @@ module byteUnit #(parameter WIDTH=32) ( assign Rev8Result[WIDTH-i-1:WIDTH-i-8] = A[i+7:i]; end - assign ByteResult = (B[0]) ? OrcBResult : Rev8Result; + assign ByteResult = (ByteSelect) ? OrcBResult : Rev8Result; endmodule \ No newline at end of file diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index 3289d13a..13529d6a 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -54,7 +54,7 @@ module zbb #(parameter WIDTH=32) ( logic [WIDTH-1:0] ExtResult; // sign/zero extend result cnt #(WIDTH) cnt(.A(A), .B(B), .W64(W64), .CntResult(CntResult)); - byteUnit #(WIDTH) bu(.A(A), .B(B), .ByteResult(ByteResult)); + byteUnit #(WIDTH) bu(.A(A), .ByteSelect(B[0]), .ByteResult(ByteResult)); ext #(WIDTH) ext(.A(A), .B(B), .ExtResult(ExtResult)); diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 7bbc8bf6..d27af3b4 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -244,7 +244,7 @@ module controller( assign ALUControlD = {W64D, SubArithD, ALUOpD}; if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags - bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, BW64D, BALUOpD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE); + bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE); end else begin: bitmanipi assign ALUSelectD = Funct3D; assign ALUSelectE = Funct3E; From 2bfbf051a5a06d19f3a72ba70ae8915bf1923d7e Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Mar 2023 11:40:29 -0800 Subject: [PATCH 03/10] zbc select mux optimization --- src/ieu/bmu/zbc.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/bmu/zbc.sv b/src/ieu/bmu/zbc.sv index 580cdacc..ad858846 100644 --- a/src/ieu/bmu/zbc.sv +++ b/src/ieu/bmu/zbc.sv @@ -66,7 +66,7 @@ module zbc #(parameter WIDTH=32) ( clmul #(WIDTH) clm(.A(x), .B(y), .ClmulResult(ClmulResult)); bitreverse #(WIDTH) brClmulResult(.a(ClmulResult), .b(RevClmulResult)); - assign ZBCResult = (Funct3 == 3'b011 || Funct3 == 3'b010) ? RevClmulResult : ClmulResult; + assign ZBCResult = (Funct3[1]) ? RevClmulResult : ClmulResult; endmodule \ No newline at end of file From 905373d53b72dc7963edf5b068bb97e2a9b39b6c Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Mar 2023 11:43:05 -0800 Subject: [PATCH 04/10] zbc input select mux optimize --- src/ieu/bmu/zbc.sv | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/ieu/bmu/zbc.sv b/src/ieu/bmu/zbc.sv index ad858846..243ed396 100644 --- a/src/ieu/bmu/zbc.sv +++ b/src/ieu/bmu/zbc.sv @@ -43,16 +43,16 @@ module zbc #(parameter WIDTH=32) ( //NOTE: Optimize this when doing decoder stuff. always_comb begin - casez (Funct3) - 3'b001: begin //clmul + casez (Funct3[1:0]) + 2'b01: begin //clmul x = A; y = B; end - 3'b011: begin //clmulh + 2'b11: begin //clmulh x = {RevA[WIDTH-2:0], {1'b0}}; y = {{1'b0}, RevB[WIDTH-2:0]}; end - 3'b010: begin //clmulr + 2'b10: begin //clmulr x = RevA; y = RevB; end From d40f3b2a1cd6714e667462d265ae294bbddd692d Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Mar 2023 11:45:32 -0800 Subject: [PATCH 05/10] rename shifternew to shifter --- src/ieu/alu.sv | 4 ++-- src/ieu/shifter.sv | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index f1bfd912..4cf8d6ed 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -106,8 +106,8 @@ module alu #(parameter WIDTH=32) ( assign CondInvB = SubArith ? ~CondMaskB : CondMaskB; assign {Carry, Sum} = CondShiftA + CondInvB + {{(WIDTH-1){1'b0}}, SubArith}; - // Shifts - shifternew sh(.shA(shA), .rotA(rotA), .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64(W64), .Y(Shift), .Rotate(Rotate)); + // Shifts (configurable for rotation) + shifter sh(.shA(shA), .rotA(rotA), .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64(W64), .Y(Shift), .Rotate(Rotate)); // Condition code flags are based on subtraction output Sum = A-B. // Overflow occurs when the numbers being subtracted have the opposite sign diff --git a/src/ieu/shifter.sv b/src/ieu/shifter.sv index f6cb5bc1..b784414b 100644 --- a/src/ieu/shifter.sv +++ b/src/ieu/shifter.sv @@ -29,7 +29,7 @@ `include "wally-config.vh" -module shifternew ( +module shifter ( input logic [`XLEN:0] shA, // shift Source input logic [`XLEN-1:0] rotA, // rotate source input logic [`LOG_XLEN-1:0] Amt, // Shift amount From 7dd4a2e9755a0534dcb493633f765724fb0bf7c6 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Mar 2023 12:15:22 -0800 Subject: [PATCH 06/10] added BRegWriteE signal --- src/ieu/bmu/bmuctrl.sv | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 7bc2bbe3..b9df2154 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -45,7 +45,8 @@ module bmuctrl( input logic StallE, FlushE, // Stall, flush Execute stage output logic [2:0] ALUSelectE, output logic [3:0] BSelectE, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding - output logic [2:0] ZBBSelectE // ZBB mux select signal + output logic [2:0] ZBBSelectE, // ZBB mux select signal + output logic BRegWriteE // Indicates if it is a R type B instruction in Execute ); logic [6:0] OpD; // Opcode in Decode stage @@ -159,5 +160,5 @@ module bmuctrl( // BMU Execute stage pipieline control register - flopenrc#(10) controlregBMU(clk, reset, FlushE, ~StallE, {ALUSelectD, BSelectD, ZBBSelectD}, {ALUSelectE, BSelectE, ZBBSelectE}); + flopenrc#(11) controlregBMU(clk, reset, FlushE, ~StallE, {ALUSelectD, BSelectD, ZBBSelectD, BRegWriteD}, {ALUSelectE, BSelectE, ZBBSelectE, BRegWriteE}); endmodule \ No newline at end of file From 1e1ecaafb18375cdfc22bca23857697571af7d6a Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Mar 2023 12:15:57 -0800 Subject: [PATCH 07/10] moved SubArith and RegWriteE into configurable block --- src/ieu/controller.sv | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index d27af3b4..549e23ad 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -114,6 +114,7 @@ module controller( logic unused; logic BranchFlagE; // Branch flag to use (chosen between eq or lt) logic IEURegWriteE; // Register write + logic BRegWriteE; // Register write from BMU controller in Execute Stage logic IllegalERegAdrD; // RV32E attempts to write upper 16 registers logic [1:0] AtomicE; // Atomic instruction logic FenceD, FenceE, FenceM; // Fence instruction @@ -240,17 +241,26 @@ module controller( assign sltuD = (Funct3D == 3'b011); assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi assign sraD = (Funct3D == 3'b101 & Funct7D[5]); - assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD)) | (`ZBB_SUPPORTED & (andnD | ornD | xnorD))); // TRUE for R-type subtracts and sra, slt, sltu, and any B instruction that requires inverted operand - assign ALUControlD = {W64D, SubArithD, ALUOpD}; + assign ALUControlD = {(W64D | BW64D), SubArithD, ALUOpD}; if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags - bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE); + bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE); + + assign RegWriteE = IEURegWriteE | FWriteIntE | BRegWriteE; // IRF register writes could come from IEU, BMU or FPU controllers + assign SubArithD = (ALUOpD | BALUOpD) & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD)) | (`ZBB_SUPPORTED & (andnD | ornD | xnorD))); // TRUE for R-type subtracts and sra, slt, sltu, and any B instruction that requires inverted operand end else begin: bitmanipi assign ALUSelectD = Funct3D; assign ALUSelectE = Funct3E; assign BSelectE = 4'b0000; assign BSelectD = 4'b0000; assign ZBBSelectE = 3'b000; + assign BRegWriteD = 1'b0; + assign BW64D = 1'b0; + assign BALUOpD = 1'b0; + assign BRegWriteE = 1'b0; + + assign RegWriteE = IEURegWriteE | FWriteIntE; // IRF register writes could come from IEU or FPU controllers + assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD); end // Fences @@ -287,7 +297,6 @@ module controller( // Other execute stage controller signals assign MemReadE = MemRWE[1]; assign SCE = (ResultSrcE == 3'b100); - assign RegWriteE = IEURegWriteE | FWriteIntE; // IRF register writes could come from IEU or FPU controllers assign IntDivE = MDUE & Funct3E[2]; // Integer division operation // Memory stage pipeline control register From 1b222f91bea4f6428591108a289cc639ee2ceea5 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Mar 2023 12:17:03 -0800 Subject: [PATCH 08/10] moved ALUControlD into configurable block --- src/ieu/controller.sv | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 549e23ad..6911f75e 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -241,13 +241,13 @@ module controller( assign sltuD = (Funct3D == 3'b011); assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi assign sraD = (Funct3D == 3'b101 & Funct7D[5]); - assign ALUControlD = {(W64D | BW64D), SubArithD, ALUOpD}; if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE); assign RegWriteE = IEURegWriteE | FWriteIntE | BRegWriteE; // IRF register writes could come from IEU, BMU or FPU controllers assign SubArithD = (ALUOpD | BALUOpD) & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD)) | (`ZBB_SUPPORTED & (andnD | ornD | xnorD))); // TRUE for R-type subtracts and sra, slt, sltu, and any B instruction that requires inverted operand + assign ALUControlD = {(W64D | BW64D), SubArithD, ALUOpD}; end else begin: bitmanipi assign ALUSelectD = Funct3D; assign ALUSelectE = Funct3E; @@ -261,6 +261,7 @@ module controller( assign RegWriteE = IEURegWriteE | FWriteIntE; // IRF register writes could come from IEU or FPU controllers assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD); + assign ALUControlD = {W64D, SubArithD, ALUOpD}; end // Fences From 2d7d143f6d0088722345e8347c425bda88e56715 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Mar 2023 13:45:15 -0800 Subject: [PATCH 09/10] formatted bmu decoder --- src/ieu/bmu/bmuctrl.sv | 108 ++++++++++++++++++++--------------------- 1 file changed, 54 insertions(+), 54 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index b9df2154..e838c6ea 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -70,85 +70,85 @@ module bmuctrl( casez({OpD, Funct7D, Funct3D}) // ALUSelect_BSelect_ZBBSelect_BRegWrite_BW64_BALUOp // ZBS - 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_101; // bclri + 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1; // bclri 17'b0010011_0100101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b111_0001_000_101; // bclri (rv64) + BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1; // bclri (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction - 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_101; // bexti + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction + 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1; // bexti 17'b0010011_0100101_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b101_0001_000_101; // bexti (rv64) + BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1; // bexti (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction - 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_101; // binvi + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction + 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1; // binvi 17'b0010011_0110101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b100_0001_000_101; // binvi (rv64) + BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1; // binvi (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction - 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_101; // bseti + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction + 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1; // bseti 17'b0010011_0010101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b110_0001_000_101; // bseti (rv64) + BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1; // bseti (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction - 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_101; // bclr - 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_101; // bext - 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_101; // binv - 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_101; // bset - 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_000_101; // sra, srai, srl, srli, sll, slli + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction + 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1; // bclr + 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1; // bext + 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1; // binv + 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1; // bset + 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_000_1_0_1; // sra, srai, srl, srli, sll, slli // ZBC - 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010_000_101; // ZBC instruction + 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010_000_1_0_1; // ZBC instruction // ZBA - 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_101; // sh1add - 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_101; // sh2add - 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_101; // sh3add - 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_111; // sh1add.uw - 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_111; // sh2add.uw - 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_111; // sh3add.uw - 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000_000_111; // add.uw - 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000_000_111; // slli.uw + 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1; // sh1add + 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1; // sh2add + 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1; // sh3add + 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1; // sh1add.uw + 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1; // sh2add.uw + 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1; // sh3add.uw + 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1; // add.uw + 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000_000_1_1_1; // slli.uw // ZBB - 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_101; // rol - 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_111; // rolw - 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_101; // ror - 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_111; // rorw - 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_101; // rori (rv32) + 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1; // rol + 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1; // rolw + 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1; // ror + 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1; // rorw + 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1; // rori (rv32) 17'b0010011_0110001_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_0100_111_101; // rori (rv64) + BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1; // rori (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction 17'b0011011_0110000_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_0100_111_111; // roriw + BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1; // roriw else - BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction 17'b0010011_0110000_001: if (Rs2D[2]) - BMUControlsD = `BMUCTRLW'b000_0100_100_101; // sign extend instruction + BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1; // sign extend instruction else - BMUControlsD = `BMUCTRLW'b000_0100_000_101; // count instruction - 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_0100_000_111; // count word instruction + BMUControlsD = `BMUCTRLW'b000_0100_000_1_0_1; // count instruction + 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_0100_000_1_1_1; // count word instruction 17'b0111011_0000100_100: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b000_0100_100_101; // zexth (rv64) + BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1; // zexth (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction 17'b0110011_0000100_100: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_0100_100_101; // zexth (rv32) + BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1; // zexth (rv32) else - BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction - 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0100_111_101; // andn - 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0100_111_101; // orn - 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0100_111_101; // xnor + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction + 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0100_111_1_0_1; // andn + 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0100_111_1_0_1; // orn + 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0100_111_1_0_1; // xnor 17'b0010011_0110101_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b000_0100_011_101; // rev8 (rv64) + BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1; // rev8 (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction 17'b0010011_0110100_101: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_0100_011_101; // rev8 (rv32) + BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1; // rev8 (rv32) else - BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction - 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_0100_011_101; // orc.b - 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0100_101_101; // max - 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0100_101_101; // maxu - 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_0100_110_101; // min - 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_0100_110_101; // minu + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction + 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1; // orc.b + 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1; // max + 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1; // maxu + 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1; // min + 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1; // minu default: BMUControlsD = {Funct3D, {10'b0}}; // not B instruction or shift endcase From b52208b53965451ca93513d5065ad86e893d839b Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Mar 2023 13:52:00 -0800 Subject: [PATCH 10/10] zbc comments --- src/ieu/bmu/zbc.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/bmu/zbc.sv b/src/ieu/bmu/zbc.sv index 243ed396..011af80e 100644 --- a/src/ieu/bmu/zbc.sv +++ b/src/ieu/bmu/zbc.sv @@ -41,7 +41,7 @@ module zbc #(parameter WIDTH=32) ( bitreverse #(WIDTH) brA(.a(A), .b(RevA)); bitreverse #(WIDTH) brB(.a(B), .b(RevB)); - //NOTE: Optimize this when doing decoder stuff. + // zbc input select mux always_comb begin casez (Funct3[1:0]) 2'b01: begin //clmul