From 1d268fded421dfd6aaaf7ded9b8ff94b08421439 Mon Sep 17 00:00:00 2001
From: Kip Macsai-Goren <kmacsaigoren@hmc.edu>
Date: Mon, 5 Dec 2022 20:14:41 -0800
Subject: [PATCH] added corrrect scr read out of uart to periph test

---
 .../privilege/references/WALLY-periph-01.reference_output     | 4 ++--
 .../riscv-test-suite/rv32i_m/privilege/src/WALLY-periph-01.S  | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-periph-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-periph-01.reference_output
index 2d17f1e7..25745a98 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-periph-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-periph-01.reference_output
@@ -440,7 +440,7 @@ FFFFFFCC # serviced low ip
 00000065
 00000060
 00000001
-00000000
+000000ff
 00000000
 00000000
 00000000
@@ -488,7 +488,7 @@ FFFFFFFE
 0000006e
 00000060
 00000001
-00000000
+000000ff
 00000000
 00000000
 00000000
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-periph-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-periph-01.S
index 418215eb..46e2483d 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-periph-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-periph-01.S
@@ -59,8 +59,8 @@ trap_handler: #####
     #
     # <offset>: <contents>
     # 0x00: test ID = 0x<group_num>BEEF<intr_num>
-    # 0x04: mcause (low)  = 0x0000000B (MEIP) or 0x00000009 (SEIP)
-    # 0x08: mcause (high) = 0x80000000
+    # 0x04: mcause (low)  = 0x8000000B (MEIP) or 0x80000009 (SEIP)
+    # 0x08: mcause (high) = 0x00000000
     # ----- If GPIO -----
     # 0x0C: claim ID = 3
     # 0x10: input_val