changed SC M-to-E fowarding to W-to-E forwarding to improve critical path

wally-pipelined/src/ieu/controller.sv

@@ -50,6 +50,7 @@ module controller(
   input  logic       StallM, FlushM,
   output logic [1:0] MemRWM,
   output logic       CSRReadM, CSRWriteM, PrivilegedM,
+  output logic       SCE,
   output logic [1:0] AtomicM,
   output logic [2:0] Funct3M,
   output logic       RegWriteM,     // for Hazard Unit
@@ -203,6 +204,7 @@ module controller(
   assign PCSrcE = JumpE | BranchE & BranchTakenE;
 
   assign MemReadE = MemRWE[1];
+  assign SCE = (ResultSrcE == 3'b100);
   
   // Memory stage pipeline control register
   flopenrc #(15) controlregM(clk, reset, FlushM, ~StallM,

wally-pipelined/src/ieu/forward.sv

@@ -32,6 +32,7 @@ module forward(
   input logic        RegWriteM, RegWriteW,
   input logic        DivDoneE, DivBusyE,
   input logic	       FWriteIntE, FWriteIntM, FWriteIntW,
+  input logic        SCE,
   // Forwarding controls
   output logic [1:0] ForwardAE, ForwardBE,
   output logic       FPUStallD, LoadStallD, MulDivStallD, CSRRdStallD
@@ -53,7 +54,7 @@ module forward(
 
   // Stall on dependent operations that finish in Mem Stage and can't bypass in time
    assign FPUStallD = FWriteIntE & ((Rs1D == RdE) | (Rs2D == RdE)); 
-   assign LoadStallD = MemReadE & ((Rs1D == RdE) | (Rs2D == RdE));  
+   assign LoadStallD = (MemReadE|SCE) & ((Rs1D == RdE) | (Rs2D == RdE));  
    assign MulDivStallD = MulDivE & ((Rs1D == RdE) | (Rs2D == RdE)) | MulDivE | DivBusyE; // *** extend with stalls for divide
    assign CSRRdStallD = CSRReadE & ((Rs1D == RdE) | (Rs2D == RdE));
 

wally-pipelined/src/ieu/ieu.sv

@@ -74,6 +74,7 @@ module ieu (
   logic        ALUSrcAE, ALUSrcBE;
   logic [2:0]  ResultSrcW;
   logic        TargetSrcE;
+  logic        SCE;
 
   // forwarding signals
   logic [4:0]       Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW;