diff --git a/wally-pipelined/src/ieu/controller.sv b/wally-pipelined/src/ieu/controller.sv
index b27541d4..3654437f 100644
--- a/wally-pipelined/src/ieu/controller.sv
+++ b/wally-pipelined/src/ieu/controller.sv
@@ -49,7 +49,8 @@ module controller(
   // Memory stage control signals
   input  logic       StallM, FlushM,
   output logic [1:0] MemRWM,
-  output logic       CSRReadM, CSRWriteM, PrivilegedM, 
+  output logic       CSRReadM, CSRWriteM, PrivilegedM,
+  output logic       SCE,
   output logic [1:0] AtomicM,
   output logic [2:0] Funct3M,
   output logic       RegWriteM,     // for Hazard Unit
@@ -202,7 +203,8 @@ module controller(
     
   assign PCSrcE = JumpE | BranchE & BranchTakenE;
 
-  assign MemReadE = MemRWE[1]; 
+  assign MemReadE = MemRWE[1];
+  assign SCE = (ResultSrcE == 3'b100);
   
   // Memory stage pipeline control register
   flopenrc #(15) controlregM(clk, reset, FlushM, ~StallM,
diff --git a/wally-pipelined/src/ieu/forward.sv b/wally-pipelined/src/ieu/forward.sv
index cdc6d270..07c4daaf 100644
--- a/wally-pipelined/src/ieu/forward.sv
+++ b/wally-pipelined/src/ieu/forward.sv
@@ -28,13 +28,14 @@
 module forward(
   // Detect hazards
   input logic [4:0]  Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW,
-  input logic 	     MemReadE, MulDivE, CSRReadE,
-  input logic 	     RegWriteM, RegWriteW,
-  input logic 	     DivDoneE, DivBusyE,
-  input logic	     FWriteIntE, FWriteIntM, FWriteIntW,
+  input logic        MemReadE, MulDivE, CSRReadE,
+  input logic        RegWriteM, RegWriteW,
+  input logic        DivDoneE, DivBusyE,
+  input logic	       FWriteIntE, FWriteIntM, FWriteIntW,
+  input logic        SCE,
   // Forwarding controls
   output logic [1:0] ForwardAE, ForwardBE,
-  output logic 	     FPUStallD, LoadStallD, MulDivStallD, CSRRdStallD
+  output logic       FPUStallD, LoadStallD, MulDivStallD, CSRRdStallD
 );
   
   always_comb begin
@@ -43,7 +44,7 @@ module forward(
     if (Rs1E != 5'b0)
       if      ((Rs1E == RdM) & RegWriteM) ForwardAE = 2'b10;
       else if ((Rs1E == RdW) & (RegWriteW|FWriteIntW)) ForwardAE = 2'b01;
-     else if ((Rs1E == RdM) & FWriteIntM) ForwardAE = 2'b11;
+      else if ((Rs1E == RdM) & FWriteIntM) ForwardAE = 2'b11;
  
     if (Rs2E != 5'b0)
       if      ((Rs2E == RdM) & RegWriteM) ForwardBE = 2'b10;
@@ -53,7 +54,7 @@ module forward(
 
   // Stall on dependent operations that finish in Mem Stage and can't bypass in time
    assign FPUStallD = FWriteIntE & ((Rs1D == RdE) | (Rs2D == RdE)); 
-   assign LoadStallD = MemReadE & ((Rs1D == RdE) | (Rs2D == RdE));  
+   assign LoadStallD = (MemReadE|SCE) & ((Rs1D == RdE) | (Rs2D == RdE));  
    assign MulDivStallD = MulDivE & ((Rs1D == RdE) | (Rs2D == RdE)) | MulDivE | DivBusyE; // *** extend with stalls for divide
    assign CSRRdStallD = CSRReadE & ((Rs1D == RdE) | (Rs2D == RdE));
 
diff --git a/wally-pipelined/src/ieu/ieu.sv b/wally-pipelined/src/ieu/ieu.sv
index 0bd9d598..62dc371b 100644
--- a/wally-pipelined/src/ieu/ieu.sv
+++ b/wally-pipelined/src/ieu/ieu.sv
@@ -73,7 +73,8 @@ module ieu (
   logic [4:0]  ALUControlE;
   logic        ALUSrcAE, ALUSrcBE;
   logic [2:0]  ResultSrcW;
-  logic       TargetSrcE;
+  logic        TargetSrcE;
+  logic        SCE;
 
   // forwarding signals
   logic [4:0]       Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW;