From 16f3c25cb7b20c85eae45c5390939c809b80ce9a Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Tue, 20 Dec 2022 02:57:51 -0800
Subject: [PATCH] sram1p1rw cleanup

---
 addins/riscv-arch-test                 |  2 +-
 pipelined/src/generic/mem/sram1p1rw.sv | 36 +++++++++++---------------
 2 files changed, 16 insertions(+), 22 deletions(-)

diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test
index e302d3ba..ee028eb3 160000
--- a/addins/riscv-arch-test
+++ b/addins/riscv-arch-test
@@ -1 +1 @@
-Subproject commit e302d3bab41a46ec388691b1d961aa09fe2a4bc4
+Subproject commit ee028eb325525148a34420a4ca7959b24220a91e
diff --git a/pipelined/src/generic/mem/sram1p1rw.sv b/pipelined/src/generic/mem/sram1p1rw.sv
index eff148cb..45668125 100644
--- a/pipelined/src/generic/mem/sram1p1rw.sv
+++ b/pipelined/src/generic/mem/sram1p1rw.sv
@@ -44,8 +44,7 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256) (
   input logic [(WIDTH-1)/8:0]     bwe,
   output logic [WIDTH-1:0]        dout);
 
-  logic [WIDTH-1:0]               RAM[DEPTH-1:0];
-
+    logic [WIDTH-1:0]               RAM[DEPTH-1:0];
 
   // ***************************************************************************
   // TRUE SRAM macro
@@ -65,29 +64,24 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256) (
   // ***************************************************************************
   // READ first SRAM model
   // ***************************************************************************
-  end else begin
+  end else begin: ram
     integer i;
-    if (WIDTH%8 != 0) // handle msbs if not a multiple of 8
+
+    // Read
+    always @(posedge clk) 
+      if(ce) dout <= #1 RAM[addr];
+ 
+    // Write divided into part for bytes and part for extra msbs
+    if(WIDTH >= 8) 
+      always @(posedge clk) 
+        if (ce & we) 
+          for(i = 0; i < WIDTH/8; i++) 
+            if(bwe[i]) RAM[addr][i*8 +: 8] <= #1 din[i*8 +: 8];
+          
+    if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8
       always @(posedge clk) 
         if (ce & we & bwe[WIDTH/8])
           RAM[addr][WIDTH-1:WIDTH-WIDTH%8] <= #1 din[WIDTH-1:WIDTH-WIDTH%8];
-
-    always @(posedge clk) begin
-      if(ce) begin
-        dout <= #1 RAM[addr];
-      end
-    end
-    if(WIDTH >= 8) begin
-      always @(posedge clk) begin
-        if(ce) begin
-          if(we) begin
-            for(i = 0; i < WIDTH/8; i++) 
-              if(bwe[i])
-		        RAM[addr][i*8 +: 8] <= #1 din[i*8 +: 8];
-          end
-        end
-      end
-    end
   end
 
 endmodule