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Fixed the timing issue in the cache replacement polcy.

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Ross Thompson 2021-10-25 18:00:23 -05:00
parent 576383c74b
commit 1228dbbebc
1 changed files with 17 additions and 4 deletions
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21
wally-pipelined/src/cache/cachereplacementpolicy.sv vendored
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@ -42,21 +42,34 @@ module cachereplacementpolicy
logic [NUMWAYS-2:0] ReplacementBits [NUMLINES-1:0]; logic [NUMWAYS-2:0] ReplacementBits [NUMLINES-1:0];
logic [NUMWAYS-2:0] BlockReplacementBits; logic [NUMWAYS-2:0] BlockReplacementBits;
logic [NUMWAYS-2:0] NewReplacement; logic [NUMWAYS-2:0] NewReplacement;
logic [NUMWAYS-2:0] NewReplacementD;
logic [INDEXLEN+OFFSETLEN-1:OFFSETLEN] MemPAdrMD;
logic [INDEXLEN-1:0] RAdrD;
logic LRUWriteEnD;
/* verilator lint_off BLKLOOPINIT */ /* verilator lint_off BLKLOOPINIT */
always_ff @(posedge clk, posedge reset) begin always_ff @(posedge clk, posedge reset) begin
if (reset) begin if (reset) begin
RAdrD <= '0;
MemPAdrMD <= '0;
LRUWriteEnD <= 0;
NewReplacementD <= '0;
for(int index = 0; index < NUMLINES; index++) for(int index = 0; index < NUMLINES; index++)
ReplacementBits[index] <= '0; ReplacementBits[index] <= '0;
end else begin end else begin
BlockReplacementBits <= ReplacementBits[RAdr]; RAdrD <= RAdr;
if (LRUWriteEn) begin MemPAdrMD <= MemPAdrMD;
ReplacementBits[MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]] <= NewReplacement; LRUWriteEnD <= LRUWriteEn;
NewReplacementD <= NewReplacement;
if (LRUWriteEnD) begin
ReplacementBits[MemPAdrMD[INDEXLEN+OFFSETLEN-1:OFFSETLEN]] <= NewReplacementD;
end end
end end
end end
/* verilator lint_on BLKLOOPINIT */ /* verilator lint_on BLKLOOPINIT */
assign BlockReplacementBits = ReplacementBits[RAdrD];
genvar index; genvar index;
generate generate