From 1228dbbebc434cc9ff2955c408686434d340e0ef Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 25 Oct 2021 18:00:23 -0500
Subject: [PATCH] Fixed the timing issue in the cache replacement polcy.

---
 .../src/cache/cachereplacementpolicy.sv       | 21 +++++++++++++++----
 1 file changed, 17 insertions(+), 4 deletions(-)

diff --git a/wally-pipelined/src/cache/cachereplacementpolicy.sv b/wally-pipelined/src/cache/cachereplacementpolicy.sv
index 8ba0c185..d2739a7c 100644
--- a/wally-pipelined/src/cache/cachereplacementpolicy.sv
+++ b/wally-pipelined/src/cache/cachereplacementpolicy.sv
@@ -42,21 +42,34 @@ module cachereplacementpolicy
   logic [NUMWAYS-2:0] 				ReplacementBits [NUMLINES-1:0];
   logic [NUMWAYS-2:0] 				BlockReplacementBits;
   logic [NUMWAYS-2:0] 				NewReplacement;
+  logic [NUMWAYS-2:0] 				NewReplacementD;  
 
+  logic [INDEXLEN+OFFSETLEN-1:OFFSETLEN] 	MemPAdrMD;
+  logic [INDEXLEN-1:0] 				RAdrD;
+  logic 					LRUWriteEnD;
+  
   /* verilator lint_off BLKLOOPINIT */
   always_ff @(posedge clk, posedge reset) begin
     if (reset) begin
+      RAdrD <= '0;
+      MemPAdrMD <= '0;
+      LRUWriteEnD <= 0;
+      NewReplacementD <= '0;
       for(int index = 0; index < NUMLINES; index++)
-	      ReplacementBits[index] <= '0;
+	ReplacementBits[index] <= '0;
     end else begin
-      BlockReplacementBits <= ReplacementBits[RAdr];
-      if (LRUWriteEn) begin
-	      ReplacementBits[MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]] <= NewReplacement;
+      RAdrD <= RAdr;
+      MemPAdrMD <= MemPAdrMD;
+      LRUWriteEnD <= LRUWriteEn;
+      NewReplacementD <= NewReplacement;
+      if (LRUWriteEnD) begin
+	ReplacementBits[MemPAdrMD[INDEXLEN+OFFSETLEN-1:OFFSETLEN]] <= NewReplacementD;
       end
     end
   end
   /* verilator lint_on BLKLOOPINIT */
 
+  assign BlockReplacementBits = ReplacementBits[RAdrD];
 
   genvar 		      index;
   generate