forked from Github_Repos/cvw
migrated B-subarith logic into b controller
This commit is contained in:
Kevin Kim
parent
b5a5f364e1
commit
11f165d1bb
@ -41,6 +41,7 @@ module bmuctrl(
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output logic BRegWriteD, // Indicates if it is a R type B instruction
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output logic BW64D, // Indiciates if it is a W type B instruction
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output logic BALUOpD, // Indicates if it is an ALU B instruction
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output logic BSubArithD, // Indicates if Bitmanip SubArith flag should be on
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output logic IllegalBitmanipInstrD, // Indicates if it is unrecognized B instruction
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// Execute stage control signals
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input logic StallE, FlushE, // Stall, flush Execute stage
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@ -55,7 +56,7 @@ module bmuctrl(
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logic [6:0] Funct7D; // Funct7 field in Decode stage
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logic [4:0] Rs2D; // Rs2 source register in Decode stage
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`define BMUCTRLW 14
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`define BMUCTRLW 15
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logic [`BMUCTRLW-1:0] BMUControlsD; // Main B Instructions Decoder control signals
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@ -69,94 +70,94 @@ module bmuctrl(
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// Main Instruction Decoder
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always_comb
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casez({OpD, Funct7D, Funct3D})
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// ALUSelect_BSelect_ZBBSelect_BRegWrite_BW64_BALUOp_IllegalBitmanipInstrD
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// ALUSelect_BSelect_ZBBSelect_BRegWrite_BW64_BALUOp_BSubArithD_IllegalBitmanipInstrD
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// ZBS
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17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_0; // bclri
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17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0; // bclri
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17'b0010011_0100101_001: if (`XLEN == 64)
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BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_0; // bclri (rv64)
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BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0; // bclri (rv64)
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else
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction
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17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_0; // bexti
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction
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17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0; // bexti
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17'b0010011_0100101_101: if (`XLEN == 64)
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BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_0; // bexti (rv64)
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BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0; // bexti (rv64)
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else
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction
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17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0; // binvi
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction
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17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0; // binvi
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17'b0010011_0110101_001: if (`XLEN == 64)
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BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0; // binvi (rv64)
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BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0; // binvi (rv64)
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else
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction
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17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0; // bseti
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction
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17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0; // bseti
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17'b0010011_0010101_001: if (`XLEN == 64)
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BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0; // bseti (rv64)
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BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0; // bseti (rv64)
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else
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction
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17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_0; // bclr
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17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_0; // bext
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17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0; // binv
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17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0; // bset
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17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_000_1_0_1_0; // sra, srai, srl, srli, sll, slli
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction
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17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0; // bclr
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17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0; // bext
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17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0; // binv
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17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0; // bset
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17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_000_1_0_1_0_0; // sra, srai, srl, srli, sll, slli
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// ZBC
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17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010_000_1_0_1_0; // ZBC instruction
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17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010_000_1_0_1_0_0; // ZBC instruction
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// ZBA
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17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0; // sh1add
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17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0; // sh2add
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17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0; // sh3add
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17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0; // sh1add.uw
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17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0; // sh2add.uw
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17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0; // sh3add.uw
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17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0; // add.uw
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17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000_000_1_1_1_0; // slli.uw
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17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0; // sh1add
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17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0; // sh2add
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17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0; // sh3add
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17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0; // sh1add.uw
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17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0; // sh2add.uw
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17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0; // sh3add.uw
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17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0; // add.uw
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17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000_000_1_1_1_0_0; // slli.uw
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// ZBB
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17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0; // rol
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17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0; // rolw
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17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0; // ror
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17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0; // rorw
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17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0; // rori (rv32)
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17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_0; // rol
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17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_0; // rolw
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17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_0; // ror
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17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_0; // rorw
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17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_0; // rori (rv32)
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17'b0010011_0110001_101: if (`XLEN == 64)
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BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0; // rori (rv64)
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BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_0; // rori (rv64)
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else
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction
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17'b0011011_0110000_101: if (`XLEN == 64)
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BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0; // roriw
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BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_0; // roriw
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else
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction
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17'b0010011_0110000_001: if (Rs2D[2])
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BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0; // sign extend instruction
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BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0; // sign extend instruction
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else
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BMUControlsD = `BMUCTRLW'b000_0100_000_1_0_1_0; // count instruction
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17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_0100_000_1_1_1_0; // count word instruction
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BMUControlsD = `BMUCTRLW'b000_0100_000_1_0_1_0_0; // count instruction
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17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_0100_000_1_1_1_0_0; // count word instruction
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17'b0111011_0000100_100: if (`XLEN == 64)
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BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0; // zexth (rv64)
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BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0; // zexth (rv64)
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else
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction
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17'b0110011_0000100_100: if (`XLEN == 32)
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BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0; // zexth (rv32)
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BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0; // zexth (rv32)
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else
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction
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17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0100_111_1_0_1_0; // andn
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17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0100_111_1_0_1_0; // orn
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17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0100_111_1_0_1_0; // xnor
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction
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17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0100_111_1_0_1_1_0; // andn
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17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0100_111_1_0_1_1_0; // orn
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17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0100_111_1_0_1_1_0; // xnor
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17'b0010011_0110101_101: if (`XLEN == 64)
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BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0; // rev8 (rv64)
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BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0; // rev8 (rv64)
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else
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction
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17'b0010011_0110100_101: if (`XLEN == 32)
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BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0; // rev8 (rv32)
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BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0; // rev8 (rv32)
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else
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction
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17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0; // orc.b
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17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0; // max
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17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0; // maxu
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17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1_0; // min
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17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1_0; // minu
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BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction
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17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0; // orc.b
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17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0_0; // max
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17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0_0; // maxu
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17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1_0_0; // min
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17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1_0_0; // minu
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default: BMUControlsD = {Funct3D, {10'b0}, {1'b1}}; // not B instruction or shift
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default: BMUControlsD = {Funct3D, {11'b0}, {1'b1}}; // not B instruction or shift
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endcase
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// Unpack Control Signals
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assign {ALUSelectD,BSelectD,ZBBSelectD, BRegWriteD, BW64D, BALUOpD, IllegalBitmanipInstrD} = BMUControlsD;
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assign {ALUSelectD,BSelectD,ZBBSelectD, BRegWriteD, BW64D, BALUOpD, BSubArithD, IllegalBitmanipInstrD} = BMUControlsD;
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@ -206,6 +206,7 @@ module controller(
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assign ALUOpD = BaseALUOpD | BALUOpD;
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assign RegWriteD = BaseRegWriteD | BRegWriteD;
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assign W64D = BaseW64D | BW64D;
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assign SubArithD = BaseSubArithD | BSubArithD; // TRUE If B-type or R-type instruction involves inverted operand
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assign CSRZeroSrcD = InstrD[14] ? (InstrD[19:15] == 0) : (Rs1D == 0); // Is a CSR instruction using zero as the source?
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@ -252,14 +253,14 @@ module controller(
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assign sltuD = (Funct3D == 3'b011);
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assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi
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assign sraD = (Funct3D == 3'b101 & Funct7D[5]);
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assign SubArithD = BaseSubArithD | BSubArithD; // TRUE If B-type or R-type instruction involves inverted operand
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assign BaseSubArithD = ALUOpD & (subD | sraD | sltD | sltuD);
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assign ALUControlD = {W64D, SubArithD, ALUOpD};
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// BITMANIP Configuration Block
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if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags
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bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .IllegalBitmanipInstrD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE);
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bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE);
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assign SubArithD = (ALUOpD) & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD)) | (`ZBB_SUPPORTED & (andnD | ornD | xnorD))); // TRUE for R-type subtracts and sra, slt, sltu, and any B instruction that requires inverted operand
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//assign SubArithD = (ALUOpD) & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD)) | (`ZBB_SUPPORTED & (andnD | ornD | xnorD))); // TRUE for R-type subtracts and sra, slt, sltu, and any B instruction that requires inverted operand
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end else begin: bitmanipi
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assign ALUSelectD = Funct3D;
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assign ALUSelectE = Funct3E;
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@ -272,7 +273,6 @@ module controller(
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assign BRegWriteE = 1'b0;
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assign BSubArithD = 1'b0;
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assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD);
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assign IllegalBitmanipInstrD = 1'b1;
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end
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