From 11f165d1bb281afb9b0dba5acacf089fbbdde0ba Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 3 Mar 2023 08:40:29 -0800 Subject: [PATCH] migrated B-subarith logic into b controller --- src/ieu/bmu/bmuctrl.sv | 117 +++++++++++++++++++++-------------------- src/ieu/controller.sv | 8 +-- 2 files changed, 63 insertions(+), 62 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 9b3e3a97..2a4a450e 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -41,6 +41,7 @@ module bmuctrl( output logic BRegWriteD, // Indicates if it is a R type B instruction output logic BW64D, // Indiciates if it is a W type B instruction output logic BALUOpD, // Indicates if it is an ALU B instruction + output logic BSubArithD, // Indicates if Bitmanip SubArith flag should be on output logic IllegalBitmanipInstrD, // Indicates if it is unrecognized B instruction // Execute stage control signals input logic StallE, FlushE, // Stall, flush Execute stage @@ -55,7 +56,7 @@ module bmuctrl( logic [6:0] Funct7D; // Funct7 field in Decode stage logic [4:0] Rs2D; // Rs2 source register in Decode stage - `define BMUCTRLW 14 + `define BMUCTRLW 15 logic [`BMUCTRLW-1:0] BMUControlsD; // Main B Instructions Decoder control signals @@ -69,94 +70,94 @@ module bmuctrl( // Main Instruction Decoder always_comb casez({OpD, Funct7D, Funct3D}) - // ALUSelect_BSelect_ZBBSelect_BRegWrite_BW64_BALUOp_IllegalBitmanipInstrD + // ALUSelect_BSelect_ZBBSelect_BRegWrite_BW64_BALUOp_BSubArithD_IllegalBitmanipInstrD // ZBS - 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_0; // bclri + 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0; // bclri 17'b0010011_0100101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_0; // bclri (rv64) + BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0; // bclri (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction - 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_0; // bexti + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction + 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0; // bexti 17'b0010011_0100101_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_0; // bexti (rv64) + BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0; // bexti (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction - 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0; // binvi + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction + 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0; // binvi 17'b0010011_0110101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0; // binvi (rv64) + BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0; // binvi (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction - 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0; // bseti + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction + 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0; // bseti 17'b0010011_0010101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0; // bseti (rv64) + BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0; // bseti (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction - 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_0; // bclr - 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_0; // bext - 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0; // binv - 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0; // bset - 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_000_1_0_1_0; // sra, srai, srl, srli, sll, slli + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction + 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0; // bclr + 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0; // bext + 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0; // binv + 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0; // bset + 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_000_1_0_1_0_0; // sra, srai, srl, srli, sll, slli // ZBC - 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010_000_1_0_1_0; // ZBC instruction + 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010_000_1_0_1_0_0; // ZBC instruction // ZBA - 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0; // sh1add - 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0; // sh2add - 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0; // sh3add - 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0; // sh1add.uw - 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0; // sh2add.uw - 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0; // sh3add.uw - 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0; // add.uw - 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000_000_1_1_1_0; // slli.uw + 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0; // sh1add + 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0; // sh2add + 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0; // sh3add + 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0; // sh1add.uw + 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0; // sh2add.uw + 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0; // sh3add.uw + 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0; // add.uw + 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000_000_1_1_1_0_0; // slli.uw // ZBB - 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0; // rol - 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0; // rolw - 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0; // ror - 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0; // rorw - 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0; // rori (rv32) + 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_0; // rol + 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_0; // rolw + 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_0; // ror + 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_0; // rorw + 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_0; // rori (rv32) 17'b0010011_0110001_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0; // rori (rv64) + BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_0; // rori (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction 17'b0011011_0110000_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0; // roriw + BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_0; // roriw else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction 17'b0010011_0110000_001: if (Rs2D[2]) - BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0; // sign extend instruction + BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0; // sign extend instruction else - BMUControlsD = `BMUCTRLW'b000_0100_000_1_0_1_0; // count instruction - 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_0100_000_1_1_1_0; // count word instruction + BMUControlsD = `BMUCTRLW'b000_0100_000_1_0_1_0_0; // count instruction + 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_0100_000_1_1_1_0_0; // count word instruction 17'b0111011_0000100_100: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0; // zexth (rv64) + BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0; // zexth (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction 17'b0110011_0000100_100: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0; // zexth (rv32) + BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0; // zexth (rv32) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction - 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0100_111_1_0_1_0; // andn - 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0100_111_1_0_1_0; // orn - 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0100_111_1_0_1_0; // xnor + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction + 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0100_111_1_0_1_1_0; // andn + 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0100_111_1_0_1_1_0; // orn + 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0100_111_1_0_1_1_0; // xnor 17'b0010011_0110101_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0; // rev8 (rv64) + BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0; // rev8 (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction 17'b0010011_0110100_101: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0; // rev8 (rv32) + BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0; // rev8 (rv32) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction - 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0; // orc.b - 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0; // max - 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0; // maxu - 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1_0; // min - 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1_0; // minu + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction + 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0; // orc.b + 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0_0; // max + 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0_0; // maxu + 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1_0_0; // min + 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1_0_0; // minu - default: BMUControlsD = {Funct3D, {10'b0}, {1'b1}}; // not B instruction or shift + default: BMUControlsD = {Funct3D, {11'b0}, {1'b1}}; // not B instruction or shift endcase // Unpack Control Signals - assign {ALUSelectD,BSelectD,ZBBSelectD, BRegWriteD, BW64D, BALUOpD, IllegalBitmanipInstrD} = BMUControlsD; + assign {ALUSelectD,BSelectD,ZBBSelectD, BRegWriteD, BW64D, BALUOpD, BSubArithD, IllegalBitmanipInstrD} = BMUControlsD; diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 0e5f3079..2cee4183 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -206,6 +206,7 @@ module controller( assign ALUOpD = BaseALUOpD | BALUOpD; assign RegWriteD = BaseRegWriteD | BRegWriteD; assign W64D = BaseW64D | BW64D; + assign SubArithD = BaseSubArithD | BSubArithD; // TRUE If B-type or R-type instruction involves inverted operand assign CSRZeroSrcD = InstrD[14] ? (InstrD[19:15] == 0) : (Rs1D == 0); // Is a CSR instruction using zero as the source? @@ -252,14 +253,14 @@ module controller( assign sltuD = (Funct3D == 3'b011); assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi assign sraD = (Funct3D == 3'b101 & Funct7D[5]); - assign SubArithD = BaseSubArithD | BSubArithD; // TRUE If B-type or R-type instruction involves inverted operand + assign BaseSubArithD = ALUOpD & (subD | sraD | sltD | sltuD); assign ALUControlD = {W64D, SubArithD, ALUOpD}; // BITMANIP Configuration Block if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags - bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .IllegalBitmanipInstrD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE); + bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE); - assign SubArithD = (ALUOpD) & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD)) | (`ZBB_SUPPORTED & (andnD | ornD | xnorD))); // TRUE for R-type subtracts and sra, slt, sltu, and any B instruction that requires inverted operand + //assign SubArithD = (ALUOpD) & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD)) | (`ZBB_SUPPORTED & (andnD | ornD | xnorD))); // TRUE for R-type subtracts and sra, slt, sltu, and any B instruction that requires inverted operand end else begin: bitmanipi assign ALUSelectD = Funct3D; assign ALUSelectE = Funct3E; @@ -272,7 +273,6 @@ module controller( assign BRegWriteE = 1'b0; assign BSubArithD = 1'b0; - assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD); assign IllegalBitmanipInstrD = 1'b1; end