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sqrt tests in regression uncommented and pass

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This commit is contained in:
Katherine Parry 2022-08-07 23:38:10 +00:00
parent 8eeca3319c
commit 0f077012c3
3 changed files with 71 additions and 71 deletions
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8
pipelined/src/fpu/srt.sv
View File

@ -142,11 +142,11 @@ module srt(
// if starting a new divison set Q to 0 and QM to -1 // if starting a new divison set Q to 0 and QM to -1
mux2 #(`DIVb+1) QMmux(QMNext[`DIVCOPIES-1], '1, DivStart, QMMux); mux2 #(`DIVb+1) QMmux(QMNext[`DIVCOPIES-1], '1, DivStart, QMMux);
flopenr #(`DIVb+1) Qreg(clk, DivStart, DivBusy, QNext[`DIVCOPIES-1], Q[0]); flopenr #(`DIVb+1) Qreg(clk, DivStart, DivBusy, QNext[`DIVCOPIES-1], Q[0]);
flopen #(`DIVb+1) QMreg(clk, DivBusy, QMMux, QM[0]); flopen #(`DIVb+1) QMreg(clk, DivStart|DivBusy, QMMux, QM[0]);
flopr #(`DIVb+1) SMreg(clk, DivStart, SMNext[`DIVCOPIES-1], SM[0]); flopenr #(`DIVb+1) SMreg(clk, DivStart, DivBusy, SMNext[`DIVCOPIES-1], SM[0]);
mux2 #(`DIVb+1) Smux(SNext[`DIVCOPIES-1], {SqrtM, {(`DIVb){1'b0}}}, DivStart, SMux); mux2 #(`DIVb+1) Smux(SNext[`DIVCOPIES-1], {1'b1, {(`DIVb){1'b0}}}, DivStart, SMux);
flop #(`DIVb+1) Sreg(clk, SMux, S[0]); flopen #(`DIVb+1) Sreg(clk, DivStart|DivBusy, SMux, S[0]);
// division takes the result from the next cycle, which is shifted to the left one more time so the square root also needs to be shifted // division takes the result from the next cycle, which is shifted to the left one more time so the square root also needs to be shifted
always_comb always_comb
if(SqrtM) // sqrt ouputs in the range (1, .5] if(SqrtM) // sqrt ouputs in the range (1, .5]

2
pipelined/src/fpu/srtfsm.sv
View File

@ -80,7 +80,7 @@ module srtfsm(
state <= #1 IDLE; state <= #1 IDLE;
end else if (DivStart&~StallE) begin end else if (DivStart&~StallE) begin
step <= Dur; step <= Dur;
if (XZeroE|YZeroE|XInfE|YInfE|XNaNE|YNaNE|(XsE&SqrtE)) state <= #1 DONE; if (XZeroE|(YZeroE&~SqrtE)|XInfE|YInfE|XNaNE|YNaNE|(XsE&SqrtE)) state <= #1 DONE;
else state <= #1 BUSY; else state <= #1 BUSY;
end else if (state == BUSY) begin end else if (state == BUSY) begin
if ((~|step[`DURLEN-1:1]&step[0])|WZero) begin if ((~|step[`DURLEN-1:1]&step[0])|WZero) begin

132
pipelined/testbench/tests.vh
View File

@ -257,16 +257,16 @@ string imperas32f[] = '{
"rv32i_m/F/FSGNJN-S-01", "rv32i_m/F/FSGNJN-S-01",
"rv32i_m/F/FSGNJ-S-01", "rv32i_m/F/FSGNJ-S-01",
"rv32i_m/F/FSGNJX-S-01", "rv32i_m/F/FSGNJX-S-01",
// "rv32i_m/F/FSQRT-S-DYN-RDN-01", "rv32i_m/F/FSQRT-S-DYN-RDN-01",
// "rv32i_m/F/FSQRT-S-DYN-RMM-01", "rv32i_m/F/FSQRT-S-DYN-RMM-01",
// "rv32i_m/F/FSQRT-S-DYN-RNE-01", "rv32i_m/F/FSQRT-S-DYN-RNE-01",
// "rv32i_m/F/FSQRT-S-DYN-RTZ-01", "rv32i_m/F/FSQRT-S-DYN-RTZ-01",
// "rv32i_m/F/FSQRT-S-DYN-RUP-01", "rv32i_m/F/FSQRT-S-DYN-RUP-01",
// "rv32i_m/F/FSQRT-S-RDN-01", "rv32i_m/F/FSQRT-S-RDN-01",
// "rv32i_m/F/FSQRT-S-RMM-01", "rv32i_m/F/FSQRT-S-RMM-01",
// "rv32i_m/F/FSQRT-S-RNE-01", "rv32i_m/F/FSQRT-S-RNE-01",
// "rv32i_m/F/FSQRT-S-RTZ-01", "rv32i_m/F/FSQRT-S-RTZ-01",
// "rv32i_m/F/FSQRT-S-RUP-01", "rv32i_m/F/FSQRT-S-RUP-01",
"rv32i_m/F/FSUB-S-DYN-RDN-01", "rv32i_m/F/FSUB-S-DYN-RDN-01",
"rv32i_m/F/FSUB-S-DYN-RMM-01", "rv32i_m/F/FSUB-S-DYN-RMM-01",
"rv32i_m/F/FSUB-S-DYN-RNE-01", "rv32i_m/F/FSUB-S-DYN-RNE-01",
@ -444,16 +444,16 @@ string imperas32f[] = '{
"rv64i_m/F/FSGNJN-S-01", "rv64i_m/F/FSGNJN-S-01",
"rv64i_m/F/FSGNJ-S-01", "rv64i_m/F/FSGNJ-S-01",
"rv64i_m/F/FSGNJX-S-01", "rv64i_m/F/FSGNJX-S-01",
// "rv64i_m/F/FSQRT-S-DYN-RDN-01", "rv64i_m/F/FSQRT-S-DYN-RDN-01",
// "rv64i_m/F/FSQRT-S-DYN-RMM-01", "rv64i_m/F/FSQRT-S-DYN-RMM-01",
// "rv64i_m/F/FSQRT-S-DYN-RNE-01", "rv64i_m/F/FSQRT-S-DYN-RNE-01",
// "rv64i_m/F/FSQRT-S-DYN-RTZ-01", "rv64i_m/F/FSQRT-S-DYN-RTZ-01",
// "rv64i_m/F/FSQRT-S-DYN-RUP-01", "rv64i_m/F/FSQRT-S-DYN-RUP-01",
// "rv64i_m/F/FSQRT-S-RDN-01", "rv64i_m/F/FSQRT-S-RDN-01",
// "rv64i_m/F/FSQRT-S-RMM-01", "rv64i_m/F/FSQRT-S-RMM-01",
// "rv64i_m/F/FSQRT-S-RNE-01", "rv64i_m/F/FSQRT-S-RNE-01",
// "rv64i_m/F/FSQRT-S-RTZ-01", "rv64i_m/F/FSQRT-S-RTZ-01",
// "rv64i_m/F/FSQRT-S-RUP-01", "rv64i_m/F/FSQRT-S-RUP-01",
"rv64i_m/F/FSUB-S-DYN-RDN-01", "rv64i_m/F/FSUB-S-DYN-RDN-01",
"rv64i_m/F/FSUB-S-DYN-RMM-01", "rv64i_m/F/FSUB-S-DYN-RMM-01",
"rv64i_m/F/FSUB-S-DYN-RNE-01", "rv64i_m/F/FSUB-S-DYN-RNE-01",
@ -625,16 +625,16 @@ string imperas32f[] = '{
"rv64i_m/D/FSGNJ-D-01", "rv64i_m/D/FSGNJ-D-01",
"rv64i_m/D/FSGNJN-D-01", "rv64i_m/D/FSGNJN-D-01",
"rv64i_m/D/FSGNJX-D-01", "rv64i_m/D/FSGNJX-D-01",
// "rv64i_m/D/FSQRT-D-DYN-RDN-01", "rv64i_m/D/FSQRT-D-DYN-RDN-01",
// "rv64i_m/D/FSQRT-D-DYN-RMM-01", "rv64i_m/D/FSQRT-D-DYN-RMM-01",
// "rv64i_m/D/FSQRT-D-DYN-RNE-01", "rv64i_m/D/FSQRT-D-DYN-RNE-01",
// "rv64i_m/D/FSQRT-D-DYN-RTZ-01", "rv64i_m/D/FSQRT-D-DYN-RTZ-01",
// "rv64i_m/D/FSQRT-D-DYN-RUP-01", "rv64i_m/D/FSQRT-D-DYN-RUP-01",
// "rv64i_m/D/FSQRT-D-RDN-01", "rv64i_m/D/FSQRT-D-RDN-01",
// "rv64i_m/D/FSQRT-D-RMM-01", "rv64i_m/D/FSQRT-D-RMM-01",
// "rv64i_m/D/FSQRT-D-RNE-01", "rv64i_m/D/FSQRT-D-RNE-01",
// "rv64i_m/D/FSQRT-D-RTZ-01", "rv64i_m/D/FSQRT-D-RTZ-01",
// "rv64i_m/D/FSQRT-D-RUP-01", "rv64i_m/D/FSQRT-D-RUP-01",
"rv64i_m/D/FSUB-D-DYN-RDN-01", "rv64i_m/D/FSUB-D-DYN-RDN-01",
"rv64i_m/D/FSUB-D-DYN-RMM-01", "rv64i_m/D/FSUB-D-DYN-RMM-01",
"rv64i_m/D/FSUB-D-DYN-RNE-01", "rv64i_m/D/FSUB-D-DYN-RNE-01",
@ -1179,15 +1179,15 @@ string imperas32f[] = '{
"rv64i_m/F/src/fsgnj_b1-01.S", "rv64i_m/F/src/fsgnj_b1-01.S",
"rv64i_m/F/src/fsgnjn_b1-01.S", "rv64i_m/F/src/fsgnjn_b1-01.S",
"rv64i_m/F/src/fsgnjx_b1-01.S", "rv64i_m/F/src/fsgnjx_b1-01.S",
// "rv64i_m/F/src/fsqrt_b1-01.S", "rv64i_m/F/src/fsqrt_b1-01.S",
// "rv64i_m/F/src/fsqrt_b20-01.S", "rv64i_m/F/src/fsqrt_b20-01.S",
// "rv64i_m/F/src/fsqrt_b2-01.S", "rv64i_m/F/src/fsqrt_b2-01.S",
// "rv64i_m/F/src/fsqrt_b3-01.S", "rv64i_m/F/src/fsqrt_b3-01.S",
// "rv64i_m/F/src/fsqrt_b4-01.S", "rv64i_m/F/src/fsqrt_b4-01.S",
// "rv64i_m/F/src/fsqrt_b5-01.S", "rv64i_m/F/src/fsqrt_b5-01.S",
// "rv64i_m/F/src/fsqrt_b7-01.S", "rv64i_m/F/src/fsqrt_b7-01.S",
// "rv64i_m/F/src/fsqrt_b8-01.S", "rv64i_m/F/src/fsqrt_b8-01.S",
// "rv64i_m/F/src/fsqrt_b9-01.S", "rv64i_m/F/src/fsqrt_b9-01.S",
"rv64i_m/F/src/fsub_b10-01.S", "rv64i_m/F/src/fsub_b10-01.S",
"rv64i_m/F/src/fsub_b1-01.S", "rv64i_m/F/src/fsub_b1-01.S",
"rv64i_m/F/src/fsub_b11-01.S", "rv64i_m/F/src/fsub_b11-01.S",
@ -1355,15 +1355,15 @@ string imperas32f[] = '{
"rv64i_m/D/src/fsgnj.d_b1-01.S", "rv64i_m/D/src/fsgnj.d_b1-01.S",
"rv64i_m/D/src/fsgnjn.d_b1-01.S", "rv64i_m/D/src/fsgnjn.d_b1-01.S",
"rv64i_m/D/src/fsgnjx.d_b1-01.S", "rv64i_m/D/src/fsgnjx.d_b1-01.S",
// "rv64i_m/D/src/fsqrt.d_b1-01.S", "rv64i_m/D/src/fsqrt.d_b1-01.S",
// "rv64i_m/D/src/fsqrt.d_b20-01.S", "rv64i_m/D/src/fsqrt.d_b20-01.S",
// "rv64i_m/D/src/fsqrt.d_b2-01.S", "rv64i_m/D/src/fsqrt.d_b2-01.S",
// "rv64i_m/D/src/fsqrt.d_b3-01.S", "rv64i_m/D/src/fsqrt.d_b3-01.S",
// "rv64i_m/D/src/fsqrt.d_b4-01.S", "rv64i_m/D/src/fsqrt.d_b4-01.S",
// "rv64i_m/D/src/fsqrt.d_b5-01.S", "rv64i_m/D/src/fsqrt.d_b5-01.S",
// "rv64i_m/D/src/fsqrt.d_b7-01.S", "rv64i_m/D/src/fsqrt.d_b7-01.S",
// "rv64i_m/D/src/fsqrt.d_b8-01.S", "rv64i_m/D/src/fsqrt.d_b8-01.S",
// "rv64i_m/D/src/fsqrt.d_b9-01.S", "rv64i_m/D/src/fsqrt.d_b9-01.S",
"rv64i_m/D/src/fssub.d_b10-01.S", "rv64i_m/D/src/fssub.d_b10-01.S",
"rv64i_m/D/src/fssub.d_b1-01.S", "rv64i_m/D/src/fssub.d_b1-01.S",
"rv64i_m/D/src/fssub.d_b11-01.S", "rv64i_m/D/src/fssub.d_b11-01.S",
@ -1536,15 +1536,15 @@ string imperas32f[] = '{
"rv32i_m/F/src/fsgnj_b1-01.S", "rv32i_m/F/src/fsgnj_b1-01.S",
"rv32i_m/F/src/fsgnjn_b1-01.S", "rv32i_m/F/src/fsgnjn_b1-01.S",
"rv32i_m/F/src/fsgnjx_b1-01.S", "rv32i_m/F/src/fsgnjx_b1-01.S",
// "rv32i_m/F/src/fsqrt_b1-01.S", "rv32i_m/F/src/fsqrt_b1-01.S",
// "rv32i_m/F/src/fsqrt_b20-01.S", "rv32i_m/F/src/fsqrt_b20-01.S",
// "rv32i_m/F/src/fsqrt_b2-01.S", "rv32i_m/F/src/fsqrt_b2-01.S",
// "rv32i_m/F/src/fsqrt_b3-01.S", "rv32i_m/F/src/fsqrt_b3-01.S",
// "rv32i_m/F/src/fsqrt_b4-01.S", "rv32i_m/F/src/fsqrt_b4-01.S",
// "rv32i_m/F/src/fsqrt_b5-01.S", "rv32i_m/F/src/fsqrt_b5-01.S",
// "rv32i_m/F/src/fsqrt_b7-01.S", "rv32i_m/F/src/fsqrt_b7-01.S",
// "rv32i_m/F/src/fsqrt_b8-01.S", "rv32i_m/F/src/fsqrt_b8-01.S",
// "rv32i_m/F/src/fsqrt_b9-01.S", "rv32i_m/F/src/fsqrt_b9-01.S",
"rv32i_m/F/src/fsub_b10-01.S", "rv32i_m/F/src/fsub_b10-01.S",
"rv32i_m/F/src/fsub_b1-01.S", "rv32i_m/F/src/fsub_b1-01.S",
"rv32i_m/F/src/fsub_b11-01.S", "rv32i_m/F/src/fsub_b11-01.S",
@ -1684,15 +1684,15 @@ string imperas32f[] = '{
"rv32i_m/D/src/fsgnj.d_b1-01.S", "rv32i_m/D/src/fsgnj.d_b1-01.S",
"rv32i_m/D/src/fsgnjn.d_b1-01.S", "rv32i_m/D/src/fsgnjn.d_b1-01.S",
"rv32i_m/D/src/fsgnjx.d_b1-01.S", "rv32i_m/D/src/fsgnjx.d_b1-01.S",
// "rv32i_m/D/src/fsqrt.d_b1-01.S", "rv32i_m/D/src/fsqrt.d_b1-01.S",
// "rv32i_m/D/src/fsqrt.d_b20-01.S", "rv32i_m/D/src/fsqrt.d_b20-01.S",
// "rv32i_m/D/src/fsqrt.d_b2-01.S", "rv32i_m/D/src/fsqrt.d_b2-01.S",
// "rv32i_m/D/src/fsqrt.d_b3-01.S", "rv32i_m/D/src/fsqrt.d_b3-01.S",
// "rv32i_m/D/src/fsqrt.d_b4-01.S", "rv32i_m/D/src/fsqrt.d_b4-01.S",
// "rv32i_m/D/src/fsqrt.d_b5-01.S", "rv32i_m/D/src/fsqrt.d_b5-01.S",
// "rv32i_m/D/src/fsqrt.d_b7-01.S", "rv32i_m/D/src/fsqrt.d_b7-01.S",
// "rv32i_m/D/src/fsqrt.d_b8-01.S", "rv32i_m/D/src/fsqrt.d_b8-01.S",
// "rv32i_m/D/src/fsqrt.d_b9-01.S", "rv32i_m/D/src/fsqrt.d_b9-01.S",
"rv32i_m/D/src/fssub.d_b10-01.S", "rv32i_m/D/src/fssub.d_b10-01.S",
"rv32i_m/D/src/fssub.d_b1-01.S", "rv32i_m/D/src/fssub.d_b1-01.S",
"rv32i_m/D/src/fssub.d_b11-01.S", "rv32i_m/D/src/fssub.d_b11-01.S",