From 0f077012c3a1198f32c54bbfd286278b7c9e1cfe Mon Sep 17 00:00:00 2001 From: Katherine Parry Date: Sun, 7 Aug 2022 23:38:10 +0000 Subject: [PATCH] sqrt tests in regression uncommented and pass --- pipelined/src/fpu/srt.sv | 8 +-- pipelined/src/fpu/srtfsm.sv | 2 +- pipelined/testbench/tests.vh | 132 +++++++++++++++++------------------ 3 files changed, 71 insertions(+), 71 deletions(-) diff --git a/pipelined/src/fpu/srt.sv b/pipelined/src/fpu/srt.sv index 0e244a22..524bb2ce 100644 --- a/pipelined/src/fpu/srt.sv +++ b/pipelined/src/fpu/srt.sv @@ -142,11 +142,11 @@ module srt( // if starting a new divison set Q to 0 and QM to -1 mux2 #(`DIVb+1) QMmux(QMNext[`DIVCOPIES-1], '1, DivStart, QMMux); flopenr #(`DIVb+1) Qreg(clk, DivStart, DivBusy, QNext[`DIVCOPIES-1], Q[0]); - flopen #(`DIVb+1) QMreg(clk, DivBusy, QMMux, QM[0]); + flopen #(`DIVb+1) QMreg(clk, DivStart|DivBusy, QMMux, QM[0]); - flopr #(`DIVb+1) SMreg(clk, DivStart, SMNext[`DIVCOPIES-1], SM[0]); - mux2 #(`DIVb+1) Smux(SNext[`DIVCOPIES-1], {SqrtM, {(`DIVb){1'b0}}}, DivStart, SMux); - flop #(`DIVb+1) Sreg(clk, SMux, S[0]); + flopenr #(`DIVb+1) SMreg(clk, DivStart, DivBusy, SMNext[`DIVCOPIES-1], SM[0]); + mux2 #(`DIVb+1) Smux(SNext[`DIVCOPIES-1], {1'b1, {(`DIVb){1'b0}}}, DivStart, SMux); + flopen #(`DIVb+1) Sreg(clk, DivStart|DivBusy, SMux, S[0]); // division takes the result from the next cycle, which is shifted to the left one more time so the square root also needs to be shifted always_comb if(SqrtM) // sqrt ouputs in the range (1, .5] diff --git a/pipelined/src/fpu/srtfsm.sv b/pipelined/src/fpu/srtfsm.sv index 7fe6b6b7..c00f1dba 100644 --- a/pipelined/src/fpu/srtfsm.sv +++ b/pipelined/src/fpu/srtfsm.sv @@ -80,7 +80,7 @@ module srtfsm( state <= #1 IDLE; end else if (DivStart&~StallE) begin step <= Dur; - if (XZeroE|YZeroE|XInfE|YInfE|XNaNE|YNaNE|(XsE&SqrtE)) state <= #1 DONE; + if (XZeroE|(YZeroE&~SqrtE)|XInfE|YInfE|XNaNE|YNaNE|(XsE&SqrtE)) state <= #1 DONE; else state <= #1 BUSY; end else if (state == BUSY) begin if ((~|step[`DURLEN-1:1]&step[0])|WZero) begin diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh index fe3bd62f..bf443ac6 100644 --- a/pipelined/testbench/tests.vh +++ b/pipelined/testbench/tests.vh @@ -257,16 +257,16 @@ string imperas32f[] = '{ "rv32i_m/F/FSGNJN-S-01", "rv32i_m/F/FSGNJ-S-01", "rv32i_m/F/FSGNJX-S-01", - // "rv32i_m/F/FSQRT-S-DYN-RDN-01", - // "rv32i_m/F/FSQRT-S-DYN-RMM-01", - // "rv32i_m/F/FSQRT-S-DYN-RNE-01", - // "rv32i_m/F/FSQRT-S-DYN-RTZ-01", - // "rv32i_m/F/FSQRT-S-DYN-RUP-01", - // "rv32i_m/F/FSQRT-S-RDN-01", - // "rv32i_m/F/FSQRT-S-RMM-01", - // "rv32i_m/F/FSQRT-S-RNE-01", - // "rv32i_m/F/FSQRT-S-RTZ-01", - // "rv32i_m/F/FSQRT-S-RUP-01", + "rv32i_m/F/FSQRT-S-DYN-RDN-01", + "rv32i_m/F/FSQRT-S-DYN-RMM-01", + "rv32i_m/F/FSQRT-S-DYN-RNE-01", + "rv32i_m/F/FSQRT-S-DYN-RTZ-01", + "rv32i_m/F/FSQRT-S-DYN-RUP-01", + "rv32i_m/F/FSQRT-S-RDN-01", + "rv32i_m/F/FSQRT-S-RMM-01", + "rv32i_m/F/FSQRT-S-RNE-01", + "rv32i_m/F/FSQRT-S-RTZ-01", + "rv32i_m/F/FSQRT-S-RUP-01", "rv32i_m/F/FSUB-S-DYN-RDN-01", "rv32i_m/F/FSUB-S-DYN-RMM-01", "rv32i_m/F/FSUB-S-DYN-RNE-01", @@ -444,16 +444,16 @@ string imperas32f[] = '{ "rv64i_m/F/FSGNJN-S-01", "rv64i_m/F/FSGNJ-S-01", "rv64i_m/F/FSGNJX-S-01", - // "rv64i_m/F/FSQRT-S-DYN-RDN-01", - // "rv64i_m/F/FSQRT-S-DYN-RMM-01", - // "rv64i_m/F/FSQRT-S-DYN-RNE-01", - // "rv64i_m/F/FSQRT-S-DYN-RTZ-01", - // "rv64i_m/F/FSQRT-S-DYN-RUP-01", - // "rv64i_m/F/FSQRT-S-RDN-01", - // "rv64i_m/F/FSQRT-S-RMM-01", - // "rv64i_m/F/FSQRT-S-RNE-01", - // "rv64i_m/F/FSQRT-S-RTZ-01", - // "rv64i_m/F/FSQRT-S-RUP-01", + "rv64i_m/F/FSQRT-S-DYN-RDN-01", + "rv64i_m/F/FSQRT-S-DYN-RMM-01", + "rv64i_m/F/FSQRT-S-DYN-RNE-01", + "rv64i_m/F/FSQRT-S-DYN-RTZ-01", + "rv64i_m/F/FSQRT-S-DYN-RUP-01", + "rv64i_m/F/FSQRT-S-RDN-01", + "rv64i_m/F/FSQRT-S-RMM-01", + "rv64i_m/F/FSQRT-S-RNE-01", + "rv64i_m/F/FSQRT-S-RTZ-01", + "rv64i_m/F/FSQRT-S-RUP-01", "rv64i_m/F/FSUB-S-DYN-RDN-01", "rv64i_m/F/FSUB-S-DYN-RMM-01", "rv64i_m/F/FSUB-S-DYN-RNE-01", @@ -625,16 +625,16 @@ string imperas32f[] = '{ "rv64i_m/D/FSGNJ-D-01", "rv64i_m/D/FSGNJN-D-01", "rv64i_m/D/FSGNJX-D-01", - // "rv64i_m/D/FSQRT-D-DYN-RDN-01", - // "rv64i_m/D/FSQRT-D-DYN-RMM-01", - // "rv64i_m/D/FSQRT-D-DYN-RNE-01", - // "rv64i_m/D/FSQRT-D-DYN-RTZ-01", - // "rv64i_m/D/FSQRT-D-DYN-RUP-01", - // "rv64i_m/D/FSQRT-D-RDN-01", - // "rv64i_m/D/FSQRT-D-RMM-01", - // "rv64i_m/D/FSQRT-D-RNE-01", - // "rv64i_m/D/FSQRT-D-RTZ-01", - // "rv64i_m/D/FSQRT-D-RUP-01", + "rv64i_m/D/FSQRT-D-DYN-RDN-01", + "rv64i_m/D/FSQRT-D-DYN-RMM-01", + "rv64i_m/D/FSQRT-D-DYN-RNE-01", + "rv64i_m/D/FSQRT-D-DYN-RTZ-01", + "rv64i_m/D/FSQRT-D-DYN-RUP-01", + "rv64i_m/D/FSQRT-D-RDN-01", + "rv64i_m/D/FSQRT-D-RMM-01", + "rv64i_m/D/FSQRT-D-RNE-01", + "rv64i_m/D/FSQRT-D-RTZ-01", + "rv64i_m/D/FSQRT-D-RUP-01", "rv64i_m/D/FSUB-D-DYN-RDN-01", "rv64i_m/D/FSUB-D-DYN-RMM-01", "rv64i_m/D/FSUB-D-DYN-RNE-01", @@ -1179,15 +1179,15 @@ string imperas32f[] = '{ "rv64i_m/F/src/fsgnj_b1-01.S", "rv64i_m/F/src/fsgnjn_b1-01.S", "rv64i_m/F/src/fsgnjx_b1-01.S", - // "rv64i_m/F/src/fsqrt_b1-01.S", - // "rv64i_m/F/src/fsqrt_b20-01.S", - // "rv64i_m/F/src/fsqrt_b2-01.S", - // "rv64i_m/F/src/fsqrt_b3-01.S", - // "rv64i_m/F/src/fsqrt_b4-01.S", - // "rv64i_m/F/src/fsqrt_b5-01.S", - // "rv64i_m/F/src/fsqrt_b7-01.S", - // "rv64i_m/F/src/fsqrt_b8-01.S", - // "rv64i_m/F/src/fsqrt_b9-01.S", + "rv64i_m/F/src/fsqrt_b1-01.S", + "rv64i_m/F/src/fsqrt_b20-01.S", + "rv64i_m/F/src/fsqrt_b2-01.S", + "rv64i_m/F/src/fsqrt_b3-01.S", + "rv64i_m/F/src/fsqrt_b4-01.S", + "rv64i_m/F/src/fsqrt_b5-01.S", + "rv64i_m/F/src/fsqrt_b7-01.S", + "rv64i_m/F/src/fsqrt_b8-01.S", + "rv64i_m/F/src/fsqrt_b9-01.S", "rv64i_m/F/src/fsub_b10-01.S", "rv64i_m/F/src/fsub_b1-01.S", "rv64i_m/F/src/fsub_b11-01.S", @@ -1355,15 +1355,15 @@ string imperas32f[] = '{ "rv64i_m/D/src/fsgnj.d_b1-01.S", "rv64i_m/D/src/fsgnjn.d_b1-01.S", "rv64i_m/D/src/fsgnjx.d_b1-01.S", - // "rv64i_m/D/src/fsqrt.d_b1-01.S", - // "rv64i_m/D/src/fsqrt.d_b20-01.S", - // "rv64i_m/D/src/fsqrt.d_b2-01.S", - // "rv64i_m/D/src/fsqrt.d_b3-01.S", - // "rv64i_m/D/src/fsqrt.d_b4-01.S", - // "rv64i_m/D/src/fsqrt.d_b5-01.S", - // "rv64i_m/D/src/fsqrt.d_b7-01.S", - // "rv64i_m/D/src/fsqrt.d_b8-01.S", - // "rv64i_m/D/src/fsqrt.d_b9-01.S", + "rv64i_m/D/src/fsqrt.d_b1-01.S", + "rv64i_m/D/src/fsqrt.d_b20-01.S", + "rv64i_m/D/src/fsqrt.d_b2-01.S", + "rv64i_m/D/src/fsqrt.d_b3-01.S", + "rv64i_m/D/src/fsqrt.d_b4-01.S", + "rv64i_m/D/src/fsqrt.d_b5-01.S", + "rv64i_m/D/src/fsqrt.d_b7-01.S", + "rv64i_m/D/src/fsqrt.d_b8-01.S", + "rv64i_m/D/src/fsqrt.d_b9-01.S", "rv64i_m/D/src/fssub.d_b10-01.S", "rv64i_m/D/src/fssub.d_b1-01.S", "rv64i_m/D/src/fssub.d_b11-01.S", @@ -1536,15 +1536,15 @@ string imperas32f[] = '{ "rv32i_m/F/src/fsgnj_b1-01.S", "rv32i_m/F/src/fsgnjn_b1-01.S", "rv32i_m/F/src/fsgnjx_b1-01.S", - // "rv32i_m/F/src/fsqrt_b1-01.S", - // "rv32i_m/F/src/fsqrt_b20-01.S", - // "rv32i_m/F/src/fsqrt_b2-01.S", - // "rv32i_m/F/src/fsqrt_b3-01.S", - // "rv32i_m/F/src/fsqrt_b4-01.S", - // "rv32i_m/F/src/fsqrt_b5-01.S", - // "rv32i_m/F/src/fsqrt_b7-01.S", - // "rv32i_m/F/src/fsqrt_b8-01.S", - // "rv32i_m/F/src/fsqrt_b9-01.S", + "rv32i_m/F/src/fsqrt_b1-01.S", + "rv32i_m/F/src/fsqrt_b20-01.S", + "rv32i_m/F/src/fsqrt_b2-01.S", + "rv32i_m/F/src/fsqrt_b3-01.S", + "rv32i_m/F/src/fsqrt_b4-01.S", + "rv32i_m/F/src/fsqrt_b5-01.S", + "rv32i_m/F/src/fsqrt_b7-01.S", + "rv32i_m/F/src/fsqrt_b8-01.S", + "rv32i_m/F/src/fsqrt_b9-01.S", "rv32i_m/F/src/fsub_b10-01.S", "rv32i_m/F/src/fsub_b1-01.S", "rv32i_m/F/src/fsub_b11-01.S", @@ -1684,15 +1684,15 @@ string imperas32f[] = '{ "rv32i_m/D/src/fsgnj.d_b1-01.S", "rv32i_m/D/src/fsgnjn.d_b1-01.S", "rv32i_m/D/src/fsgnjx.d_b1-01.S", - // "rv32i_m/D/src/fsqrt.d_b1-01.S", - // "rv32i_m/D/src/fsqrt.d_b20-01.S", - // "rv32i_m/D/src/fsqrt.d_b2-01.S", - // "rv32i_m/D/src/fsqrt.d_b3-01.S", - // "rv32i_m/D/src/fsqrt.d_b4-01.S", - // "rv32i_m/D/src/fsqrt.d_b5-01.S", - // "rv32i_m/D/src/fsqrt.d_b7-01.S", - // "rv32i_m/D/src/fsqrt.d_b8-01.S", - // "rv32i_m/D/src/fsqrt.d_b9-01.S", + "rv32i_m/D/src/fsqrt.d_b1-01.S", + "rv32i_m/D/src/fsqrt.d_b20-01.S", + "rv32i_m/D/src/fsqrt.d_b2-01.S", + "rv32i_m/D/src/fsqrt.d_b3-01.S", + "rv32i_m/D/src/fsqrt.d_b4-01.S", + "rv32i_m/D/src/fsqrt.d_b5-01.S", + "rv32i_m/D/src/fsqrt.d_b7-01.S", + "rv32i_m/D/src/fsqrt.d_b8-01.S", + "rv32i_m/D/src/fsqrt.d_b9-01.S", "rv32i_m/D/src/fssub.d_b10-01.S", "rv32i_m/D/src/fssub.d_b1-01.S", "rv32i_m/D/src/fssub.d_b11-01.S",