forked from Github_Repos/cvw
Starting to parameterize
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src/wally/cvw.sv
136
src/wally/cvw.sv
@ -31,11 +31,11 @@
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package cvw;
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typedef struct packed {
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logic [7:0] XLEN;
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logic FPGA;
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logic QEMU;
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logic [63:0] AHBW;
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logic [63:0] PA_BITS;
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byte XLEN; // Machine width (32 or 64)
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byte FPGA; // Modifications to tare
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byte QEMU; // Hacks to agree with QEMU during Linux boot
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byte AHBW; // AHB bus width (usually = XLEN)
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byte PA_BITS; // size of physical address
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logic [31:0] MISA;
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logic BUS_SUPPORTED;
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logic ZICSR_SUPPORTED;
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@ -48,6 +48,132 @@ typedef struct packed {
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logic [7:0] VPN_SEGMENT_BITS;
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} cvw_t;
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`define FPGA 0
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`define QEMU 0
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// RV32 or RV64: XLEN = 32 or 64
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`define XLEN 32
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// IEEE 754 compliance
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`define IEEE754 0
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// E
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`define MISA (32'h00000010)
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`define ZICSR_SUPPORTED 0
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`define ZIFENCEI_SUPPORTED 0
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`define COUNTERS 0
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`define ZICOUNTERS_SUPPORTED 0
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`define ZFH_SUPPORTED 0
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`define SSTC_SUPPORTED 0
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// LSU microarchitectural Features
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`define BUS_SUPPORTED 1
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`define DCACHE_SUPPORTED 0
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`define ICACHE_SUPPORTED 0
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`define VIRTMEM_SUPPORTED 0
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`define VECTORED_INTERRUPTS_SUPPORTED 0
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`define BIGENDIAN_SUPPORTED 0
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// TLB configuration. Entries should be a power of 2
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`define ITLB_ENTRIES 0
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`define DTLB_ENTRIES 0
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// Cache configuration. Sizes should be a power of two
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// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
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`define DCACHE_NUMWAYS 4
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`define DCACHE_WAYSIZEINBYTES 4096
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`define DCACHE_LINELENINBITS 512
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`define ICACHE_NUMWAYS 4
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`define ICACHE_WAYSIZEINBYTES 4096
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`define ICACHE_LINELENINBITS 512
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// Integer Divider Configuration
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// IDIV_BITSPERCYCLE must be 1, 2, or 4
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`define IDIV_BITSPERCYCLE 1
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`define IDIV_ON_FPU 0
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// Legal number of PMP entries are 0, 16, or 64
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`define PMP_ENTRIES 0
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// Address space
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`define RESET_VECTOR 32'h80000000
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// WFI Timeout Wait
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`define WFI_TIMEOUT_BIT 16
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// Peripheral Addresses
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// Peripheral memory space extends from BASE to BASE+RANGE
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// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
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`define DTIM_SUPPORTED 1'b0
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`define DTIM_BASE 34'h80000000
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`define DTIM_RANGE 34'h007FFFFF
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`define IROM_SUPPORTED 1'b0
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`define IROM_BASE 34'h80000000
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`define IROM_RANGE 34'h007FFFFF
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`define BOOTROM_SUPPORTED 1'b1
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`define BOOTROM_BASE 34'h00001000
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`define BOOTROM_RANGE 34'h00000FFF
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`define UNCORE_RAM_SUPPORTED 1'b1
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`define UNCORE_RAM_BASE 34'h80000000
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`define UNCORE_RAM_RANGE 34'h07FFFFFF
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`define EXT_MEM_SUPPORTED 1'b0
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`define EXT_MEM_BASE 34'h80000000
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`define EXT_MEM_RANGE 34'h07FFFFFF
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`define CLINT_SUPPORTED 1'b0
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`define CLINT_BASE 34'h02000000
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`define CLINT_RANGE 34'h0000FFFF
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`define GPIO_SUPPORTED 1'b0
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`define GPIO_BASE 34'h10060000
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`define GPIO_RANGE 34'h000000FF
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`define UART_SUPPORTED 1'b0
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`define UART_BASE 34'h10000000
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`define UART_RANGE 34'h00000007
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`define PLIC_SUPPORTED 1'b0
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`define PLIC_BASE 34'h0C000000
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`define PLIC_RANGE 34'h03FFFFFF
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`define SDC_SUPPORTED 1'b0
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`define SDC_BASE 34'h00012100
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`define SDC_RANGE 34'h0000001F
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// Bus Interface width
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`define AHBW 32
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// Test modes
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// Tie GPIO outputs back to inputs
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`define GPIO_LOOPBACK_TEST 1
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// Hardware configuration
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`define UART_PRESCALE 1
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// Interrupt configuration
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`define PLIC_NUM_SRC 10
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// comment out the following if >=32 sources
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`define PLIC_NUM_SRC_LT_32
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`define PLIC_GPIO_ID 3
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`define PLIC_UART_ID 10
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`define BPRED_SUPPORTED 0
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`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
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`define BPRED_SIZE 10
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`define BTB_SIZE 10
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`define SVADU_SUPPORTED 0
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`define ZMMUL_SUPPORTED 0
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// FPU division architecture
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`define RADIX 32'h4
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`define DIVCOPIES 32'h4
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// bit manipulation
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`define ZBA_SUPPORTED 0
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`define ZBB_SUPPORTED 0
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`define ZBC_SUPPORTED 0
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`define ZBS_SUPPORTED 0
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// Memory synthesis configuration
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`define USE_SRAM 0
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/*
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// constants defining different privilege modes
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// defined in Table 1.1 of the privileged spec
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