worked out some bugs with int div cycles

pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv

@@ -104,7 +104,7 @@ module fdivsqrtfsm(
   always_comb begin 
     if (SqrtE) fbits = Nf + 2 + 2; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2
     else       fbits = Nf + 2 + `LOGR; // Nf + two fractional bits for round/guard + integer bits - try this when placing results in msbs
-    cycles =  MDUE ? nE : (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES);
+    cycles =  MDUE ? (nE + 1) : (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES);
   end 
 
   /* verilator lint_on WIDTH */

pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv

@@ -130,7 +130,7 @@ module fdivsqrtpostproc(
       NormShiftM = (mM + (`DIVBLEN+1)'(`DIVa));
       PreResultM = IntRemM;
     end else begin
-      NormShiftM = ((`DIVBLEN+1)'(`DIVb) - (nM << `LOGR));
+      NormShiftM = ((`DIVBLEN+1)'(`DIVb) - (nM * (`DIVBLEN+1)'(`LOGR)));
       PreResultM = {3'b000, IntQuotM};
     end
   

pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv

@@ -60,7 +60,7 @@ module fdivsqrtpreproc (
   logic  [`DIVBLEN:0] mE;
   logic  [`DIVBLEN:0] ZeroDiff, IntBits, RightShiftX;
   logic  [`DIVBLEN:0] pPlusr, pPrCeil, p, ell;
-  logic  [`LOGRK-1:0] pPrTrunc;
+  logic  [`LOGRK:0] pPrTrunc;
   logic  [`DIVb+3:0]  PreShiftX;
   logic  NumZeroE;
 
@@ -91,12 +91,16 @@ module fdivsqrtpreproc (
   assign ALTBE = ZeroDiff[`DIVBLEN]; // A less than B
   assign p = ALTBE ? '0 : ZeroDiff;
 
+/* verilator lint_off WIDTH */
   assign pPlusr = (`DIVBLEN)'(`LOGR) + p;
-  assign pPrTrunc = pPlusr[`LOGRK-1:0];
+  assign pPrTrunc = pPlusr % `RK;
+//assign pPrTrunc = (`LOGRK == 0) ? 0 : pPlusr[`LOGRK-1:0];
   assign pPrCeil = (pPlusr >> `LOGRK) + {{`DIVBLEN{1'b0}}, |(pPrTrunc)};
-  assign nE = (pPrCeil << `LOGK) - 1;
+  assign nE = (pPrCeil * (`DIVBLEN+1)'(`DIVCOPIES)) - {{(`DIVBLEN){1'b0}}, 1'b1};
-  assign IntBits = (`DIVBLEN)'(`RK) + p;
+  assign IntBits = (`DIVBLEN)'(`LOGR) + p - {{(`DIVBLEN){1'b0}}, 1'b1};
-  assign RightShiftX = (`DIVBLEN)'(`RK) - {{(`DIVBLEN-`RK){1'b0}}, IntBits[`RK-1:0]};
+  assign RightShiftX = ((`DIVBLEN)'(`RK) - 1) - (IntBits % `RK);
+//assign RightShiftX = (`LOGRK == 0) ? 0 : ((`DIVBLEN)'(`RK) - 1) - {{(`DIVBLEN - `RK){1'b0}}, IntBits[`LOGRK-1:0]};
+/* verilator lint_on WIDTH */
 
   assign NumZeroE = MDUE ? AZeroE : XZeroE;