From 0716aedbd5e43f7e1a398f58ada198ea111ac77f Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 11 Dec 2022 16:28:11 -0600 Subject: [PATCH] Removed unused flushf. --- pipelined/src/hazard/hazard.sv | 3 +-- pipelined/src/ifu/bpred.sv | 4 ++-- pipelined/src/ifu/ifu.sv | 4 ++-- pipelined/src/ifu/localHistoryPredictor.sv | 4 ++-- pipelined/src/wally/wallypipelinedcore.sv | 6 +++--- 5 files changed, 10 insertions(+), 11 deletions(-) diff --git a/pipelined/src/hazard/hazard.sv b/pipelined/src/hazard/hazard.sv index 0bd5cbe4..b2279560 100644 --- a/pipelined/src/hazard/hazard.sv +++ b/pipelined/src/hazard/hazard.sv @@ -41,7 +41,7 @@ module hazard( (* mark_debug = "true" *) input logic wfiM, IntPendingM, // Stall & flush outputs (* mark_debug = "true" *) output logic StallF, StallD, StallE, StallM, StallW, -(* mark_debug = "true" *) output logic FlushF, FlushD, FlushE, FlushM, FlushW +(* mark_debug = "true" *) output logic FlushD, FlushE, FlushM, FlushW ); logic StallFCause, StallDCause, StallECause, StallMCause, StallWCause; @@ -89,7 +89,6 @@ module hazard( assign FirstUnstalledW = ~StallW & StallM; // Each stage flushes if the previous stage is the last one stalled (for cause) or the system has reason to flush - assign #1 FlushF = BPPredWrongE; assign #1 FlushD = FirstUnstalledD | TrapM | RetM | BPPredWrongE; assign #1 FlushE = FirstUnstalledE | TrapM | RetM | BPPredWrongE; // *** why is BPPredWrongE here, but not needed in simple processor assign #1 FlushM = FirstUnstalledM | TrapM | RetM; diff --git a/pipelined/src/ifu/bpred.sv b/pipelined/src/ifu/bpred.sv index 2e306dc6..908d9a6b 100644 --- a/pipelined/src/ifu/bpred.sv +++ b/pipelined/src/ifu/bpred.sv @@ -36,7 +36,7 @@ module bpred (input logic clk, reset, input logic StallF, StallD, StallE, StallM, - input logic FlushF, FlushD, FlushE, FlushM, + input logic FlushD, FlushE, FlushM, // Fetch stage // the prediction input logic [31:0] InstrD, @@ -103,7 +103,7 @@ module bpred else if (`BPTYPE == "BPLOCALPAg") begin:Predictor localHistoryPredictor DirPredictor(.clk, - .reset, .StallF, .StallE, .FlushF, + .reset, .StallF, .StallE, .LookUpPC(PCNextF), .Prediction(BPPredF), // update diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 24f6f363..e7851d8b 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -34,7 +34,7 @@ module ifu ( input logic clk, reset, input logic StallF, StallD, StallE, StallM, - input logic FlushF, FlushD, FlushE, FlushM, FlushW, + input logic FlushD, FlushE, FlushM, FlushW, // Bus interface (* mark_debug = "true" *) input logic [`XLEN-1:0] HRDATA, (* mark_debug = "true" *) output logic [`PA_BITS-1:0] IFUHADDR, @@ -309,7 +309,7 @@ module ifu ( logic [`XLEN-1:0] BPPredPCF; bpred bpred(.clk, .reset, .StallF, .StallD, .StallE, .StallM, - .FlushF, .FlushD, .FlushE, .FlushM, + .FlushD, .FlushE, .FlushM, .InstrD, .PCNextF, .BPPredPCF, .SelBPPredF, .PCE, .PCSrcE, .IEUAdrE, .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .BPPredWrongM, .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM); diff --git a/pipelined/src/ifu/localHistoryPredictor.sv b/pipelined/src/ifu/localHistoryPredictor.sv index 836bca9a..75798586 100644 --- a/pipelined/src/ifu/localHistoryPredictor.sv +++ b/pipelined/src/ifu/localHistoryPredictor.sv @@ -38,7 +38,7 @@ module localHistoryPredictor ) (input logic clk, input logic reset, - input logic StallF, StallE, FlushF, + input logic StallF, StallE, input logic [`XLEN-1:0] LookUpPC, output logic [1:0] Prediction, // update @@ -116,7 +116,7 @@ module localHistoryPredictor flopenrc #(k) LHRFReg(.clk(clk), .reset(reset), .en(~StallF), - .clear(FlushF), + .clear(1'b0), .d(ForwardLHRNext), .q(LHRF)); /* diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index d189a0b1..07608885 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -53,7 +53,7 @@ module wallypipelinedcore ( // logic [1:0] ForwardAE, ForwardBE; logic StallF, StallD, StallE, StallM, StallW; - logic FlushF, FlushD, FlushE, FlushM, FlushW; + logic FlushD, FlushE, FlushM, FlushW; logic RetM; (* mark_debug = "true" *) logic TrapM; @@ -170,7 +170,7 @@ module wallypipelinedcore ( ifu ifu( .clk, .reset, .StallF, .StallD, .StallE, .StallM, - .FlushF, .FlushD, .FlushE, .FlushM, .FlushW, + .FlushD, .FlushE, .FlushM, .FlushW, // Fetch .HRDATA, .PCF, .IFUHADDR, .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE, @@ -325,7 +325,7 @@ module wallypipelinedcore ( .wfiM, .IntPendingM, // Stall & flush outputs .StallF, .StallD, .StallE, .StallM, .StallW, - .FlushF, .FlushD, .FlushE, .FlushM, .FlushW + .FlushD, .FlushE, .FlushM, .FlushW ); // global stall and flush control if (`ZICSR_SUPPORTED) begin:priv