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Hint to optimize ifu

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This commit is contained in:
David Harris 2021-01-28 21:40:48 -05:00
parent 12c6006f07
commit 05b755958f
2 changed files with 5 additions and 3 deletions
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2
riscv-o3

@ -1 +1 @@
Subproject commit a13ac64fa50c187ffd489cdb2f4a4a70e60fc837 Subproject commit afb27bd558a9b6fabb6b768ae81ef122b4db9eea

6
wally-pipelined/src/ifu.sv
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@ -106,8 +106,10 @@ module ifu (
flopr #(`XLEN) PCMReg(clk, reset, PCE, PCM); flopr #(`XLEN) PCMReg(clk, reset, PCE, PCM);
flopr #(`XLEN) PCWReg(clk, reset, PCM, PCW); // *** probably not needed; delete later flopr #(`XLEN) PCWReg(clk, reset, PCM, PCW); // *** probably not needed; delete later
// seems like there should be a lower-cost way of doing this PC+2 or PC+4 for JAL. Maybe a way to draw on PC // seems like there should be a lower-cost way of doing this PC+2 or PC+4 for JAL.
// or just put an adder at the start of the writeback stage. // either have ALU compute PC+2/4 and feed into ALUResult input of ResultMux or
// have dedicated adder in Mem stage based on PCM + 2 or 4
// *** redo this
flopr #(`XLEN) PCPDReg(clk, reset, PCPlus2or4F, PCLinkD); flopr #(`XLEN) PCPDReg(clk, reset, PCPlus2or4F, PCLinkD);
flopr #(`XLEN) PCPEReg(clk, reset, PCLinkD, PCLinkE); flopr #(`XLEN) PCPEReg(clk, reset, PCLinkD, PCLinkE);
flopr #(`XLEN) PCPMReg(clk, reset, PCLinkE, PCLinkM); flopr #(`XLEN) PCPMReg(clk, reset, PCLinkE, PCLinkM);