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Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors

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slmnemo 2022-06-08 15:03:15 -07:00
parent 284e0395a0
commit 054cf5f7b0
6 changed files with 57 additions and 68 deletions
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64
pipelined/src/ebu/ahblite.sv
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@ -45,10 +45,10 @@ module ahblite (
input logic IFUBusRead, input logic IFUBusRead,
output logic [`XLEN-1:0] IFUBusHRDATA, output logic [`XLEN-1:0] IFUBusHRDATA,
output logic IFUBusAck, output logic IFUBusAck,
output logic IFUBusLock, output logic IFUBusInit,
input logic [2:0] IFUBurstType, input logic [2:0] IFUBurstType,
input logic [1:0] IFUTransType, input logic [1:0] IFUTransType,
input logic IFUBurstDone, input logic IFUTransComplete,
// Signals from Data Cache // Signals from Data Cache
input logic [`PA_BITS-1:0] LSUBusAdr, input logic [`PA_BITS-1:0] LSUBusAdr,
input logic LSUBusRead, input logic LSUBusRead,
@ -58,9 +58,9 @@ module ahblite (
input logic [2:0] LSUBusSize, input logic [2:0] LSUBusSize,
input logic [2:0] LSUBurstType, input logic [2:0] LSUBurstType,
input logic [1:0] LSUTransType, input logic [1:0] LSUTransType,
input logic LSUBurstDone, input logic LSUTransComplete,
output logic LSUBusAck, output logic LSUBusAck,
output logic LSUBusLock, output logic LSUBusInit,
// AHB-Lite external signals // AHB-Lite external signals
(* mark_debug = "true" *) input logic [`AHBW-1:0] HRDATA, (* mark_debug = "true" *) input logic [`AHBW-1:0] HRDATA,
(* mark_debug = "true" *) input logic HREADY, HRESP, (* mark_debug = "true" *) input logic HREADY, HRESP,
@ -79,11 +79,10 @@ module ahblite (
(* mark_debug = "true" *) output logic HWRITED (* mark_debug = "true" *) output logic HWRITED
); );
typedef enum logic [2:0] {IDLE, MEMREAD, MEMREADNEXT, MEMWRITE, MEMWRITENEXT, INSTRREAD, INSTRREADNEXT} statetype; typedef enum logic [1:0] {IDLE, MEMREAD, MEMWRITE, INSTRREAD} statetype;
statetype BusState, NextBusState; statetype BusState, NextBusState;
logic GrantData; logic GrantData;
logic SubsequentAccess;
logic [31:0] AccessAddress; logic [31:0] AccessAddress;
logic [2:0] ISize; logic [2:0] ISize;
@ -112,38 +111,27 @@ module ahblite (
// interface that might be used in place of the ahblite. // interface that might be used in place of the ahblite.
always_comb always_comb
case (BusState) case (BusState)
IDLE: if (LSUBusRead) NextBusState = MEMREAD; // Memory has priority over instructions IDLE: if (LSUBusRead) NextBusState = MEMREAD; // Memory has priority over instructions
else if (LSUBusWrite)NextBusState = MEMWRITE; else if (LSUBusWrite) NextBusState = MEMWRITE;
else if (IFUBusRead) NextBusState = INSTRREAD; else if (IFUBusRead) NextBusState = INSTRREAD;
else NextBusState = IDLE; else NextBusState = IDLE;
MEMREAD: if (HREADY) NextBusState = MEMREADNEXT; MEMREAD: if (LSUTransComplete & ~IFUBusRead) NextBusState = INSTRREAD;
else NextBusState = MEMREAD; else if (LSUTransComplete) NextBusState = IDLE;
MEMREADNEXT: if (LSUBurstDone & ~(IFUBusRead & ~HREADY)) NextBusState = IDLE; else NextBusState = MEMREAD;
else if (LSUBurstDone & IFUBusRead & HREADY) NextBusState = INSTRREAD; MEMWRITE: if (LSUTransComplete & IFUBusRead) NextBusState = INSTRREAD;
else if (HREADY) NextBusState = MEMREADNEXT; else if (LSUTransComplete) NextBusState = IDLE;
else NextBusState = MEMREAD; else NextBusState = MEMWRITE;
MEMWRITE: if (HREADY) NextBusState = MEMWRITENEXT; INSTRREAD: if (IFUTransComplete & LSUBusRead) NextBusState = MEMREAD;
else NextBusState = MEMWRITE; else if (IFUTransComplete & LSUBusWrite) NextBusState = MEMWRITE;
MEMWRITENEXT: if (LSUBurstDone & ~(IFUBusRead & ~HREADY)) NextBusState = IDLE; else if (IFUTransComplete) NextBusState = IDLE;
else if (LSUBurstDone & IFUBusRead & HREADY) NextBusState = INSTRREAD; else NextBusState = INSTRREAD;
else if (HREADY) NextBusState = MEMWRITENEXT; default: NextBusState = IDLE;
else NextBusState = MEMWRITE;
INSTRREAD: if (HREADY) NextBusState = INSTRREADNEXT;
else NextBusState = INSTRREAD;
INSTRREADNEXT: if (IFUBurstDone & ~LSUBusRead & ~LSUBusWrite) NextBusState = IDLE;
else if (IFUBurstDone & LSUBusRead & HREADY) NextBusState = MEMREAD;
else if (IFUBurstDone & LSUBusWrite & HREADY) NextBusState = MEMWRITE;
else if (HREADY) NextBusState = INSTRREADNEXT;
else NextBusState = INSTRREAD;
default: NextBusState = IDLE;
endcase endcase
// bus outputs // bus outputs
assign #1 GrantData = (NextBusState == MEMREAD) | (NextBusState == MEMWRITE) | assign #1 GrantData = (NextBusState == MEMREAD) | (NextBusState == MEMWRITE);
(NextBusState == MEMREADNEXT) | (NextBusState == MEMWRITENEXT);
assign #1 AccessAddress = (GrantData) ? LSUBusAdr[31:0] : IFUBusAdr[31:0]; assign #1 AccessAddress = (GrantData) ? LSUBusAdr[31:0] : IFUBusAdr[31:0];
assign #1 SubsequentAccess = (GrantData) ? |(AccessAddress[$clog2(`XLEN):0]) : |(AccessAddress[5:0]);
assign #1 HADDR = AccessAddress; assign #1 HADDR = AccessAddress;
assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway
assign HSIZE = (GrantData) ? {1'b0, LSUBusSize[1:0]} : ISize; assign HSIZE = (GrantData) ? {1'b0, LSUBusSize[1:0]} : ISize;
@ -165,7 +153,7 @@ module ahblite (
assign HPROT = 4'b0011; // not used; see Section 3.7 assign HPROT = 4'b0011; // not used; see Section 3.7
assign HTRANS = (GrantData) ? LSUTransType : IFUTransType; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise assign HTRANS = (GrantData) ? LSUTransType : IFUTransType; // SEQ if not first read or write, NONSEQ if first read or write, IDLE otherwise
assign HMASTLOCK = 0; // no locking supported assign HMASTLOCK = 0; // no locking supported
assign HWRITE = (NextBusState == MEMWRITE) | (NextBusState == MEMWRITENEXT); assign HWRITE = (NextBusState == MEMWRITE);
// delay write data by one cycle for // delay write data by one cycle for
flopen #(`XLEN) wdreg(HCLK, (IFUBusAck | LSUBusAck), LSUBusHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN flopen #(`XLEN) wdreg(HCLK, (IFUBusAck | LSUBusAck), LSUBusHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
// delay signals for subword writes // delay signals for subword writes
@ -179,9 +167,9 @@ module ahblite (
assign IFUBusHRDATA = HRDATA; assign IFUBusHRDATA = HRDATA;
assign LSUBusHRDATA = HRDATA; assign LSUBusHRDATA = HRDATA;
assign IFUBusLock = (NextBusState == INSTRREAD) | (NextBusState == INSTRREADNEXT); assign IFUBusInit = (NextBusState == INSTRREAD);
assign LSUBusLock = (NextBusState == MEMWRITENEXT) | (NextBusState == MEMREADNEXT) | (NextBusState == MEMREAD) | (NextBusState == MEMWRITE); assign LSUBusInit = (NextBusState == MEMREAD) | (NextBusState == MEMWRITE);
assign IFUBusAck = (BusState == INSTRREADNEXT); assign IFUBusAck = HREADY & (BusState == INSTRREAD);
assign LSUBusAck = (BusState == MEMREADNEXT) | (BusState == MEMWRITENEXT); assign LSUBusAck = HREADY & ((BusState == MEMREAD) | (BusState == MEMWRITE));
endmodule endmodule

8
pipelined/src/ifu/ifu.sv
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@ -38,13 +38,13 @@ module ifu (
// Bus interface // Bus interface
(* mark_debug = "true" *) input logic [`XLEN-1:0] IFUBusHRDATA, (* mark_debug = "true" *) input logic [`XLEN-1:0] IFUBusHRDATA,
(* mark_debug = "true" *) input logic IFUBusAck, (* mark_debug = "true" *) input logic IFUBusAck,
(* mark_debug = "true" *) input logic IFUBusLock, (* mark_debug = "true" *) input logic IFUBusInit,
(* mark_debug = "true" *) output logic [`PA_BITS-1:0] IFUBusAdr, (* mark_debug = "true" *) output logic [`PA_BITS-1:0] IFUBusAdr,
(* mark_debug = "true" *) output logic IFUBusRead, (* mark_debug = "true" *) output logic IFUBusRead,
(* mark_debug = "true" *) output logic IFUStallF, (* mark_debug = "true" *) output logic IFUStallF,
(* mark_debug = "true" *) output logic [2:0] IFUBurstType, (* mark_debug = "true" *) output logic [2:0] IFUBurstType,
(* mark_debug = "true" *) output logic [1:0] IFUTransType, (* mark_debug = "true" *) output logic [1:0] IFUTransType,
(* mark_debug = "true" *) output logic IFUBurstDone, (* mark_debug = "true" *) output logic IFUTransComplete,
(* mark_debug = "true" *) output logic [`XLEN-1:0] PCF, (* mark_debug = "true" *) output logic [`XLEN-1:0] PCF,
// Execute // Execute
output logic [`XLEN-1:0] PCLinkE, output logic [`XLEN-1:0] PCLinkE,
@ -205,8 +205,8 @@ module ifu (
busdp #(WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) busdp #(WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
busdp(.clk, .reset, busdp(.clk, .reset,
.LSUBusHRDATA(IFUBusHRDATA), .LSUBusAck(IFUBusAck), .LSUBusLock(IFUBusLock), .LSUBusWrite(), .LSUBusWriteCrit(), .LSUBusHRDATA(IFUBusHRDATA), .LSUBusAck(IFUBusAck), .LSUBusInit(IFUBusInit), .LSUBusWrite(), .LSUBusWriteCrit(),
.LSUBusRead(IFUBusRead), .LSUBusSize(), .LSUBurstType(IFUBurstType), .LSUTransType(IFUTransType), .LSUBurstDone(IFUBurstDone), .LSUBusRead(IFUBusRead), .LSUBusSize(), .LSUBurstType(IFUBurstType), .LSUTransType(IFUTransType), .LSUTransComplete(IFUTransComplete),
.LSUFunct3M(3'b010), .LSUBusAdr(IFUBusAdr), .DCacheBusAdr(ICacheBusAdr), .LSUFunct3M(3'b010), .LSUBusAdr(IFUBusAdr), .DCacheBusAdr(ICacheBusAdr),
.WordCount(), .WordCount(),
.DCacheFetchLine(ICacheFetchLine), .DCacheFetchLine(ICacheFetchLine),

8
pipelined/src/lsu/busdp.sv
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@ -40,13 +40,13 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
// bus interface // bus interface
input logic [`XLEN-1:0] LSUBusHRDATA, input logic [`XLEN-1:0] LSUBusHRDATA,
input logic LSUBusAck, input logic LSUBusAck,
input logic LSUBusLock, input logic LSUBusInit,
output logic LSUBusWrite, output logic LSUBusWrite,
output logic LSUBusRead, output logic LSUBusRead,
output logic [2:0] LSUBusSize, output logic [2:0] LSUBusSize,
output logic [2:0] LSUBurstType, output logic [2:0] LSUBurstType,
output logic [1:0] LSUTransType, // For AHBLite output logic [1:0] LSUTransType, // For AHBLite
output logic LSUBurstDone, output logic LSUTransComplete,
input logic [2:0] LSUFunct3M, input logic [2:0] LSUFunct3M,
output logic [`PA_BITS-1:0] LSUBusAdr, // ** change name to HADDR to make ahb lite. output logic [`PA_BITS-1:0] LSUBusAdr, // ** change name to HADDR to make ahb lite.
output logic [LOGWPL-1:0] WordCount, output logic [LOGWPL-1:0] WordCount,
@ -89,6 +89,6 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
busfsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) busfsm( busfsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) busfsm(
.clk, .reset, .IgnoreRequest, .LSURWM, .DCacheFetchLine, .DCacheWriteLine, .clk, .reset, .IgnoreRequest, .LSURWM, .DCacheFetchLine, .DCacheWriteLine,
.LSUBusAck, .LSUBusLock, .CPUBusy, .CacheableM, .BusStall, .LSUBusWrite, .LSUBusWriteCrit, .LSUBusRead, .LSUBusAck, .LSUBusInit, .CPUBusy, .CacheableM, .BusStall, .LSUBusWrite, .LSUBusWriteCrit, .LSUBusRead,
.LSUBurstType, .LSUTransType, .LSUBurstDone, .DCacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount, .WordCountDelayed); .LSUBurstType, .LSUTransType, .LSUTransComplete, .DCacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount, .WordCountDelayed);
endmodule endmodule

15
pipelined/src/lsu/busfsm.sv
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@ -41,7 +41,7 @@ module busfsm #(parameter integer WordCountThreshold,
input logic DCacheFetchLine, input logic DCacheFetchLine,
input logic DCacheWriteLine, input logic DCacheWriteLine,
input logic LSUBusAck, input logic LSUBusAck,
input logic LSUBusLock, input logic LSUBusInit,
input logic CPUBusy, input logic CPUBusy,
input logic CacheableM, input logic CacheableM,
@ -50,7 +50,7 @@ module busfsm #(parameter integer WordCountThreshold,
output logic LSUBusWriteCrit, output logic LSUBusWriteCrit,
output logic LSUBusRead, output logic LSUBusRead,
output logic [2:0] LSUBurstType, output logic [2:0] LSUBurstType,
output logic LSUBurstDone, output logic LSUTransComplete,
output logic [1:0] LSUTransType, output logic [1:0] LSUTransType,
output logic DCacheBusAck, output logic DCacheBusAck,
output logic BusCommittedM, output logic BusCommittedM,
@ -98,7 +98,7 @@ module busfsm #(parameter integer WordCountThreshold,
assign NextWordCount = WordCount + 1'b1; assign NextWordCount = WordCount + 1'b1;
assign WordCountFlag = (WordCountDelayed == WordCountThreshold[LOGWPL-1:0]); assign WordCountFlag = (WordCountDelayed == WordCountThreshold[LOGWPL-1:0]);
assign CntEn = PreCntEn & LSUBusAck | ((DCacheFetchLine | DCacheWriteLine) & LSUBusLock); assign CntEn = (PreCntEn & LSUBusAck | (LSUBusInit)) & ~WordCountFlag;
assign UnCachedAccess = ~CACHE_ENABLED | ~CacheableM; assign UnCachedAccess = ~CACHE_ENABLED | ~CacheableM;
@ -134,16 +134,17 @@ module busfsm #(parameter integer WordCountThreshold,
always_comb begin always_comb begin
case(WordCountThreshold) case(WordCountThreshold)
1: LocalBurstType = 3'b000;
3: LocalBurstType = 3'b011; // INCR4 3: LocalBurstType = 3'b011; // INCR4
7: LocalBurstType = 3'b101; // INCR8 7: LocalBurstType = 3'b101; // INCR8
15: LocalBurstType = 3'b111; // INCR16 15: LocalBurstType = 3'b111; // INCR16
default: LocalBurstType = 3'b000; // No Burst default: LocalBurstType = 3'b001; // No Burst
endcase endcase
end end
assign LSUBurstType = (UnCachedAccess) ? 3'b0 : LocalBurstType ; // Don't want to use burst when doing an Uncached Access assign LSUBurstType = (UnCachedAccess) ? 3'b0 : LocalBurstType ; // Don't want to use burst when doing an Uncached Access.
assign LSUBurstDone = (UnCachedAccess) ? LSUBusAck : WordCountFlag & LSUBusAck; assign LSUTransComplete = (UnCachedAccess) ? LSUBusAck : WordCountFlag & LSUBusAck;
assign LSUTransType = (|WordCount | |WordCountDelayed) ? 2'b11 : (LSUBusRead | LSUBusWrite) ? 2'b10 : 2'b00; assign LSUTransType = (|WordCount) & ~UncachedAccess ? 2'b11 : (LSUBusRead | LSUBusWrite) & ~WordCountFlag ? 2'b10 : 2'b00;
assign CntReset = BusCurrState == STATE_BUS_READY & ~(DCacheFetchLine | DCacheWriteLine); assign CntReset = BusCurrState == STATE_BUS_READY & ~(DCacheFetchLine | DCacheWriteLine);
assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((UnCachedAccess & (|LSURWM)) | DCacheFetchLine | DCacheWriteLine)) | assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((UnCachedAccess & (|LSURWM)) | DCacheFetchLine | DCacheWriteLine)) |

6
pipelined/src/lsu/lsu.sv
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@ -66,13 +66,13 @@ module lsu (
(* mark_debug = "true" *) output logic LSUBusRead, (* mark_debug = "true" *) output logic LSUBusRead,
(* mark_debug = "true" *) output logic LSUBusWrite, (* mark_debug = "true" *) output logic LSUBusWrite,
(* mark_debug = "true" *) input logic LSUBusAck, (* mark_debug = "true" *) input logic LSUBusAck,
(* mark_debug = "true" *) input logic LSUBusLock, (* mark_debug = "true" *) input logic LSUBusInit,
(* mark_debug = "true" *) input logic [`XLEN-1:0] LSUBusHRDATA, (* mark_debug = "true" *) input logic [`XLEN-1:0] LSUBusHRDATA,
(* mark_debug = "true" *) output logic [`XLEN-1:0] LSUBusHWDATA, (* mark_debug = "true" *) output logic [`XLEN-1:0] LSUBusHWDATA,
(* mark_debug = "true" *) output logic [2:0] LSUBusSize, (* mark_debug = "true" *) output logic [2:0] LSUBusSize,
(* mark_debug = "true" *) output logic [2:0] LSUBurstType, (* mark_debug = "true" *) output logic [2:0] LSUBurstType,
(* mark_debug = "true" *) output logic [1:0] LSUTransType, (* mark_debug = "true" *) output logic [1:0] LSUTransType,
(* mark_debug = "true" *) output logic LSUBurstDone, (* mark_debug = "true" *) output logic LSUTransComplete,
// page table walker // page table walker
input logic [`XLEN-1:0] SATP_REGW, // from csr input logic [`XLEN-1:0] SATP_REGW, // from csr
input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV,
@ -215,7 +215,7 @@ module lsu (
busdp #(WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) busdp( busdp #(WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED) busdp(
.clk, .reset, .clk, .reset,
.LSUBusHRDATA, .LSUBusAck, .LSUBusLock, .LSUBusWrite, .LSUBusRead, .LSUBusSize, .LSUBurstType, .LSUTransType, .LSUBurstDone, .LSUBusHRDATA, .LSUBusAck, .LSUBusInit, .LSUBusWrite, .LSUBusRead, .LSUBusSize, .LSUBurstType, .LSUTransType, .LSUTransComplete,
.WordCount, .LSUBusWriteCrit, .WordCount, .LSUBusWriteCrit,
.LSUFunct3M, .LSUBusAdr, .DCacheBusAdr, .DCacheFetchLine, .LSUFunct3M, .LSUBusAdr, .DCacheBusAdr, .DCacheFetchLine,
.DCacheWriteLine, .DCacheBusAck, .DCacheBusWriteData, .LSUPAdrM, .DCacheWriteLine, .DCacheBusAck, .DCacheBusWriteData, .LSUPAdrM,

24
pipelined/src/wally/wallypipelinedcore.sv
View File

@ -134,16 +134,16 @@ module wallypipelinedcore (
logic [`PA_BITS-1:0] IFUBusAdr; logic [`PA_BITS-1:0] IFUBusAdr;
logic [`XLEN-1:0] IFUBusHRDATA; logic [`XLEN-1:0] IFUBusHRDATA;
logic IFUBusRead; logic IFUBusRead;
logic IFUBusAck, IFUBusLock; logic IFUBusAck, IFUBusInit;
logic [2:0] IFUBurstType; logic [2:0] IFUBurstType;
logic [1:0] IFUTransType; logic [1:0] IFUTransType;
logic IFUBurstDone; logic IFUTransComplete;
// AHB LSU interface // AHB LSU interface
logic [`PA_BITS-1:0] LSUBusAdr; logic [`PA_BITS-1:0] LSUBusAdr;
logic LSUBusRead; logic LSUBusRead;
logic LSUBusWrite; logic LSUBusWrite;
logic LSUBusAck, LSUBusLock; logic LSUBusAck, LSUBusInit;
logic [`XLEN-1:0] LSUBusHRDATA; logic [`XLEN-1:0] LSUBusHRDATA;
logic [`XLEN-1:0] LSUBusHWDATA; logic [`XLEN-1:0] LSUBusHWDATA;
@ -157,7 +157,7 @@ module wallypipelinedcore (
logic [2:0] LSUBusSize; logic [2:0] LSUBusSize;
logic [2:0] LSUBurstType; logic [2:0] LSUBurstType;
logic [1:0] LSUTransType; logic [1:0] LSUTransType;
logic LSUBurstDone; logic LSUTransComplete;
logic DCacheMiss; logic DCacheMiss;
logic DCacheAccess; logic DCacheAccess;
@ -172,8 +172,8 @@ module wallypipelinedcore (
.StallF, .StallD, .StallE, .StallM, .StallF, .StallD, .StallE, .StallM,
.FlushF, .FlushD, .FlushE, .FlushM, .FlushF, .FlushD, .FlushE, .FlushM,
// Fetch // Fetch
.IFUBusHRDATA, .IFUBusAck, .IFUBusLock, .PCF, .IFUBusAdr, .IFUBusHRDATA, .IFUBusAck, .IFUBusInit, .PCF, .IFUBusAdr,
.IFUBusRead, .IFUStallF, .IFUBurstType, .IFUTransType, .IFUBurstDone, .IFUBusRead, .IFUStallF, .IFUBurstType, .IFUTransType, .IFUTransComplete,
.ICacheAccess, .ICacheMiss, .ICacheAccess, .ICacheMiss,
// Execute // Execute
@ -253,8 +253,8 @@ module wallypipelinedcore (
.IEUAdrE, .IEUAdrM, .WriteDataE, .IEUAdrE, .IEUAdrM, .WriteDataE,
.ReadDataM, .FlushDCacheM, .ReadDataM, .FlushDCacheM,
// connected to ahb (all stay the same) // connected to ahb (all stay the same)
.LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusAck, .LSUBusLock, .LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusAck, .LSUBusInit,
.LSUBusHRDATA, .LSUBusHWDATA, .LSUBusSize, .LSUBurstType, .LSUTransType, .LSUBurstDone, .LSUBusHRDATA, .LSUBusHWDATA, .LSUBusSize, .LSUBurstType, .LSUTransType, .LSUTransComplete,
// connect to csr or privilege and stay the same. // connect to csr or privilege and stay the same.
.PrivilegeModeW, .BigEndianM, // connects to csr .PrivilegeModeW, .BigEndianM, // connects to csr
@ -289,18 +289,18 @@ module wallypipelinedcore (
.IFUBusHRDATA, .IFUBusHRDATA,
.IFUBurstType, .IFUBurstType,
.IFUTransType, .IFUTransType,
.IFUBurstDone, .IFUTransComplete,
.IFUBusAck, .IFUBusAck,
.IFUBusLock, .IFUBusInit,
// Signals from Data Cache // Signals from Data Cache
.LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusHWDATA, .LSUBusAdr, .LSUBusRead, .LSUBusWrite, .LSUBusHWDATA,
.LSUBusHRDATA, .LSUBusHRDATA,
.LSUBusSize, .LSUBusSize,
.LSUBurstType, .LSUBurstType,
.LSUTransType, .LSUTransType,
.LSUBurstDone, .LSUTransComplete,
.LSUBusAck, .LSUBusAck,
.LSUBusLock, .LSUBusInit,
.HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn,
.HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST,