From 043f1e10c5dc9a630fc22f68851d632f6ec24cee Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 3 Jul 2021 15:51:25 -0500 Subject: [PATCH] Added explicit names to lsu, lsuarb and pagetable walker to make the code refactoring process eaiser. --- wally-pipelined/src/lsu/lsu.sv | 16 +-- .../src/wally/wallypipelinedhart.sv | 125 ++++++++++++++---- 2 files changed, 109 insertions(+), 32 deletions(-) diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 36d4715f..36d85907 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -66,7 +66,7 @@ module lsu ( input logic MemAckW, // from ahb input logic [`XLEN-1:0] HRDATAW, // from ahb output logic [2:0] Funct3MfromLSU, - output logic StallWfromLSU, + output logic StallWfromLSU, // mmu management @@ -85,14 +85,14 @@ module lsu ( output logic DTLBHitM, // not connected // PMA/PMP (inside mmu) signals - input logic [31:0] HADDR, // *** replace all of these H inputs with physical adress once pma checkers have been edited to use paddr as well. - input logic [2:0] HSIZE, HBURST, - input logic HWRITE, - input var logic [63:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES/8-1:0], - input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], // *** this one especially has a large note attached to it in pmpchecker. + input logic [31:0] HADDR, // *** replace all of these H inputs with physical adress once pma checkers have been edited to use paddr as well. + input logic [2:0] HSIZE, HBURST, + input logic HWRITE, + input var logic [63:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES/8-1:0], + input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], // *** this one especially has a large note attached to it in pmpchecker. - output logic PMALoadAccessFaultM, PMAStoreAccessFaultM, - output logic PMPLoadAccessFaultM, PMPStoreAccessFaultM, // *** can these be parameterized? we dont need the m stage ones for the immu and vice versa. + output logic PMALoadAccessFaultM, PMAStoreAccessFaultM, + output logic PMPLoadAccessFaultM, PMPStoreAccessFaultM, // *** can these be parameterized? we dont need the m stage ones for the immu and vice versa. output logic DSquashBusAccessM // output logic [5:0] DHSELRegionsM diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index 978f747f..47035ec6 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -122,8 +122,8 @@ module wallypipelinedhart logic PMPInstrAccessFaultF, PMPLoadAccessFaultM, PMPStoreAccessFaultM; logic PMAInstrAccessFaultF, PMALoadAccessFaultM, PMAStoreAccessFaultM; logic DSquashBusAccessM, ISquashBusAccessF; - var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0]; - var logic [63:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES/8-1:0]; + var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0]; + var logic [63:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES/8-1:0]; // IMem stalls logic ICacheStallF; @@ -187,10 +187,38 @@ module wallypipelinedhart // mux2 #(`XLEN) OutputInput2mux(WriteDataM, FWriteDataM, FMemRWM[0], WriteDatatmpM); - pagetablewalker pagetablewalker(.HPTWRead(HPTWRead), - .*); // can send addresses to ahblite, send out pagetablestall + pagetablewalker pagetablewalker( + .clk(clk), + .reset(reset), + .SATP_REGW(SATP_REGW), // already on lsu port + .PCF(PCF), // add to lsu port + .MemAdrM(MemAdrM), // alreayd on lsu port + .ITLBMissF(ITLBMissF), // add to lsu port + .DTLBMissM(DTLBMissM), // already on lsu port convert to internal + .MemRWM(MemRWM), // already on lsu port + .PageTableEntryF(PageTableEntryF), // add to lsu port + .PageTableEntryM(PageTableEntryM), // already on lsu port convert to internal + .PageTypeF(PageTypeF), // add to lsu port connects to ifu + .PageTypeM(PageTypeM), + .ITLBWriteF(ITLBWriteF), + .DTLBWriteM(DTLBWriteM), + .MMUReadPTE(MMUReadPTE), + .MMUReady(MMUReady), + .HPTWStall(HPTWStall), + .MMUPAdr(MMUPAdr), + .MMUTranslate(MMUTranslate), + .HPTWRead(HPTWRead), + .MMUStall(MMUStall), + .WalkerInstrPageFaultF(WalkerInstrPageFaultF), + .WalkerLoadPageFaultM(WalkerLoadPageFaultM), + .WalkerStorePageFaultM(WalkerStorePageFaultM)); + + + // arbiter between IEU and pagetablewalker - lsuArb arbiter(// HPTW connection + lsuArb arbiter(.clk(clk), + .reset(reset), + // HPTW connection .HPTWTranslate(MMUTranslate), .HPTWRead(HPTWRead), .HPTWPAdr(MMUPAdr), @@ -202,8 +230,8 @@ module wallypipelinedhart .Funct3M(Funct3M), .AtomicM(AtomicM), .MemAdrM(MemAdrM), - .StallW(StallW), .WriteDataM(WriteDataM), + .StallW(StallW), .ReadDataW(ReadDataW), .CommittedM(CommittedM), .SquashSCW(SquashSCW), @@ -222,29 +250,78 @@ module wallypipelinedhart .DataMisalignedMfromLSU(DataMisalignedMfromLSU), .ReadDataWFromLSU(ReadDataWFromLSU), .HPTWReadyfromLSU(HPTWReadyfromLSU), - .DataStall(DataStall), - .*); + .DataStall(DataStall)); - lsu lsu(.MemRWM(MemRWMtoLSU), - .Funct3M(Funct3MtoLSU), - .AtomicM(AtomicMtoLSU), - .MemAdrM(MemAdrMtoLSU), - .WriteDataM(WriteDataMtoLSU), - .ReadDataW(ReadDataWFromLSU), + lsu lsu(.clk(clk), + .reset(reset), + .StallM(StallM), + .FlushM(FlushM), .StallW(StallWtoLSU), + .FlushW(FlushW), + // connected to arbiter (reconnect to CPU) + .MemRWM(MemRWMtoLSU), // change to MemRWM + .Funct3M(Funct3MtoLSU), // change to Funct3M + .AtomicM(AtomicMtoLSU), // change to AtomicMtoLSU + .CommittedM(CommittedMfromLSU), // change to CommitttedM + .SquashSCW(SquashSCWfromLSU), // change to SquashSCW + .DataMisalignedM(DataMisalignedMfromLSU), // change to DataMisalignedM + .MemAdrM(MemAdrMtoLSU), // change to MemAdrM + .WriteDataM(WriteDataMtoLSU), // change to WriteDataM + .ReadDataW(ReadDataWFromLSU), // change to ReadDataW - .CommittedM(CommittedMfromLSU), - .SquashSCW(SquashSCWfromLSU), - .DataMisalignedM(DataMisalignedMfromLSU), - .DisableTranslation(DisableTranslation), + // connected to ahb (all stay the same) + .CommitM(CommitM), + .MemPAdrM(MemPAdrM), + .MemReadM(MemReadM), + .MemWriteM(MemWriteM), + .AtomicMaskedM(AtomicMaskedM), + .MemAckW(MemAckW), + .HRDATAW(HRDATAW), + .Funct3MfromLSU(Funct3MfromLSU), // stays the same + .StallWfromLSU(StallWfromLSU), // stays the same + .DSquashBusAccessM(DSquashBusAccessM), // probalby removed after dcache implemenation? + // currently not connected (but will need to be used for lsu talking to ahb. + .HADDR(HADDR), + .HSIZE(HSIZE), + .HBURST(HBURST), + .HWRITE(HWRITE), + + // connect to csr or privilege and stay the same. + .PrivilegeModeW(PrivilegeModeW), // connects to csr + .PMPCFG_ARRAY_REGW(PMPCFG_ARRAY_REGW), // connects to csr + .PMPADDR_ARRAY_REGW(PMPADDR_ARRAY_REGW), // connects to csr + // hptw keep i/o + .SATP_REGW(SATP_REGW), // from csr + .STATUS_MXR(STATUS_MXR), // from csr + .STATUS_SUM(STATUS_SUM), // from csr + + .DTLBFlushM(DTLBFlushM), // connects to privilege + .NonBusTrapM(NonBusTrapM), // connects to privilege + .DTLBLoadPageFaultM(DTLBLoadPageFaultM), // connects to privilege + .DTLBStorePageFaultM(DTLBStorePageFaultM), // connects to privilege + .LoadMisalignedFaultM(LoadMisalignedFaultM), // connects to privilege + .LoadAccessFaultM(LoadAccessFaultM), // connects to privilege + .StoreMisalignedFaultM(StoreMisalignedFaultM), // connects to privilege + .StoreAccessFaultM(StoreAccessFaultM), // connects to privilege + .PMALoadAccessFaultM(PMALoadAccessFaultM), + .PMAStoreAccessFaultM(PMAStoreAccessFaultM), + .PMPLoadAccessFaultM(PMPLoadAccessFaultM), + .PMPStoreAccessFaultM(PMPStoreAccessFaultM), + + // connected to hptw. Move to internal. + .PageTableEntryM(PageTableEntryM), + .PageTypeM(PageTypeM), + .DTLBWriteM(DTLBWriteM), // from hptw. + .DTLBMissM(DTLBMissM), // to hptw from dmmu + .DisableTranslation(DisableTranslation), // from hptw to dmmu + .HPTWReady(HPTWReadyfromLSU), // from hptw, remove + + .DTLBHitM(DTLBHitM), // not connected remove + + .DataStall(DataStall)) // change to DCacheStall + ; - .DataStall(DataStall), - .HPTWReady(HPTWReadyfromLSU), - .Funct3MfromLSU(Funct3MfromLSU), - .StallWfromLSU(StallWfromLSU), -// .DataStall(LSUStall), - .* ); // data cache unit ahblite ebu( //.InstrReadF(1'b0),