forked from Github_Repos/cvw
fixing coremark branch prediction
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d0ddb5f461
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041439c008
@ -93,7 +93,7 @@ add wave -divider RAM
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add wave -hex -r /testbench/dut/uncore/dtim/RAM
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add wave -hex -r /testbench/dut/uncore/dtim/RAM
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add wave -divider Misc
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add wave -divider Misc
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add wave -divider
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add wave -divider
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#add wave -hex -r /testbench/*
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add wave -hex -r /testbench/*
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-- Set Wave Output Items
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-- Set Wave Output Items
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TreeUpdate [SetDefaultTree]
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TreeUpdate [SetDefaultTree]
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@ -111,5 +111,6 @@ set DefaultRadix hexadecimal
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-- Run the Simulation
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-- Run the Simulation
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#run 7402000
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#run 7402000
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#run 12750
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#run 12750
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run -all
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#run -all
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run 3000
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#quit
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#quit
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@ -92,6 +92,12 @@ module testbench();
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end
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end
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end
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end
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initial begin
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$readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.DirPredictor.memory.memory);
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$readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.TargetPredictor.memory.memory);
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end
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endmodule
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endmodule
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/* verilator lint_on STMTDLY */
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/* verilator lint_on STMTDLY */
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/* verilator lint_on WIDTH */
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/* verilator lint_on WIDTH */
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